- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2069 > FSA8009UMX (Fairchild Semiconductor)IC AUDIO JACK DETECTOR/SW 10UMLP PDF資料下載
參數(shù)資料
| 型號： | FSA8009UMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 0K |
| 描述： | IC AUDIO JACK DETECTOR/SW 10UMLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 音頻插孔探測器，帶視頻開關(guān) |
| 應(yīng)用： | MP3 播放器，便攜式媒體播放器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-UFQFN |
| 供應(yīng)商設(shè)備封裝： | 10-uMLP（1.4x1.8） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FSA8009UMXDKR |
6
Precision Edge
SY89534/35L
Micrel, Inc.
M9999-110308
hbwhelp@micrel.com or (408) 955-1690
AC ELECTRICAL CHARACTERISTICS
TA = 0
°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
fIN
Reference Input Frequency
———
14
—
160
———
MHz
fOUT
Output Frequency Range
———
33.33
—
500
———
MHz
tVCO
Internal VCO Frequency Range
600
—
1000
600
—
1000
600
—
1000
MHz
tskew
Within Device(11)
Within Bank
—
25
50
—
050
—
050
ps
Bank-to-Bank
—
60
150
—
60
150
—
60
150
ps
Part-to-Part Skew(12)
—————
200
——
200
ps
tLOCK
Maximum PLL Lock Time
—————
10
——
10
ms
tJITTER
Cycle-to-Cycle Jitter(13) (Pk-to-Pk)
—————
50
———
ps
Period Jitter(14)
(rms)
——
50
——
50
——
50
ps
tpw (min)
Minimum Pulse Width
———
50
——
50
——
ns
Target PLL Loop Bandwidth
Feedback Divider Ratio: 66(15)
—
1.0
——
1.0
——
1.0
—
MHz
Feedback Divider Ratio: 30(15)
—
2.0
——
2.0
——
2.0
—
MHz
tDC
fOUT Duty Cycle
———
45
50
55
45
50
55
%
tr, tf
Output Rise/Fall Time
ps
(20% to 80%)
LVPECL_Out
——
400
—
250
400
——
400
(SY89535L) LVDS_Out
——
450
—
300
450
——
450
tOUTPUT_RESET
(16)
—————
10
———
ns
tHOLD_FSEL
(16)
———
5
—————
ns
tSETUP_FSEL
(16)
———
5
—————
ns
tOUTPUT_SYNC
(16)
———
1
—————
VCO
clock cycle
FSEL-to-Valid Output Transition Time
————
50
————
ns
All VCC pins = +3.3V ±10%
NOTES:
11. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
12. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
13. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn–Tn+1
where T is the time between rising edges of the output signal.
14. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and Tn is defined as the average period of that
signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to Tn. Parameter guaranteed by
design and characterization.
15. Using recommended loop filter components.
16. See
“Timing Diagrams."
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FSA8049UCX | IC AUDIO JACK DETECT SW 9-WLCSP |
| FSA805UMX | IC AUDIO SWITCH USB 3:1 12UMLP |
| FSLV16211MTD | IC SWITCH BUS 24BIT HS 56-TSSOP |
| FST16211G | IC SWITCH BUS 24BIT TTL 54FBGA |
| FST16233MEAX | MUX/DEMUX 16-32BIT SYNC 56SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FSA800UMX | 功能描述:電源開關(guān) IC - USB USB2.0 HI Speed Switch RoHS:否 制造商:Micrel 電源電壓-最小:2.7 V 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| FSA801 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:USB2.0 High-Speed (480 Mbps), UART, and Audio Switch with Negative Signal Capability |
| FSA801UMX | 功能描述:開關(guān) IC - 各種 USB2.0 Hi-Spd UART Audio Sw/Neg Signal RoHS:否 制造商:Fairchild Semiconductor 開啟電阻（最大值）: 電源電壓-最大:4.4 V 電源電壓-最小:2.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WLCSP-9 封裝:Reel |
| FSA801UMX_F113 | 功能描述:開關(guān) IC - 各種 USB 480Mbs Audio SW RoHS:否 制造商:Fairchild Semiconductor 開啟電阻（最大值）: 電源電壓-最大:4.4 V 電源電壓-最小:2.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WLCSP-9 封裝:Reel |
| FSA8028UMX | 功能描述:開關(guān) IC - 各種 Audio Jack Detection Configuration Switch RoHS:否 制造商:Fairchild Semiconductor 開啟電阻（最大值）: 電源電壓-最大:4.4 V 電源電壓-最小:2.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:WLCSP-9 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。