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參數(shù)資料
| 型號： | FS7140-02G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 17/17頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
FS7140, FS7145
http://onsemi.com
9
If either a STOP or a repeated START condition occurs
during a register write, the data that has been transferred is
ignored.
Random Register Read Procedure
Random read operations allow the master to directly read
from any register. To perform a read procedure, the R/W bit
that is transmitted after the sevenbit address is a logiclow,
as in the register write procedure. This indicates to the
addressed slave device that a register address will follow
after the slave device acknowledges its device address. The
register address is then written into the slave’s address
pointer.
Following an acknowledge by the slave, the master
generates a repeated START condition. The repeated
START terminates the write procedure, but not until after the
slave’s address pointer is set. The slave address is then
resent, with the R/W bit set this time to a logichigh,
indicating to the slave that data will be read. The slave will
acknowledge the device address, and then transmits the
eightbit word. The master does not acknowledge the
transfer but does generate a STOP condition.
Sequential Register Write Procedure
Sequential write operations allow the master to write to
each register in order. The register pointer is automatically
incremented after each write. This procedure is more
efficient than the random register write if several registers
must be written.
To initiate a write procedure, the R/W bit that is
transmitted after the sevenbit device address is a logiclow.
This indicates to the addressed slave device that a register
address will follow after the slave device acknowledges its
device address. The register address is written into the
slave’s address pointer. Following an acknowledge by the
slave, the master is allowed to write up to eight bytes of data
into the addressed register before the register address pointer
overflows back to the beginning address.
An acknowledge by the device between each byte of data
must occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not wait
for the STOP condition to occur. Registers are therefore
updated at different times during a sequential register write.
Sequential Register Read Procedure
Sequential read operations allow the master to read from
each register in order. The register pointer is automatically
incremented by one after each read. This procedure is more
efficient than the random register read if several registers
must be read.
To perform a read procedure, the R/W bit that is
transmitted after the sevenbit address is a logiclow, as in
the register write procedure. This indicates to the addressed
slave device that a register address will follow after the slave
device acknowledges its device address. The register
address is then written into the slave’s address pointer.
Following an acknowledge by the slave, the master
generates a repeated START condition. The repeated
START terminates the write procedure, but not until after the
slave’s address pointer is set. The slave address is then
resent, with the R/W bit set this time to a logichigh,
indicating to the slave that data will be read. The slave will
acknowledge the device address, and then transmits all eight
bytes of data starting with the initial addressed register. The
register address pointer will overflow if the initial register
address is larger than zero. After the last byte of data, the
master does not acknowledge the transfer but does generate
a STOP condition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS7140-802 | 制造商:AMI Semiconductor 功能描述: |
| FS7145 | 制造商:AMI 制造商全稱:AMI 功能描述:Programmable Phase-Locked Loop Clock Generator |
| FS7145-01-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PLL CLOCK 3.3V RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS7145-01-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PLL CLOCK 3.3V RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS7145-02G | 制造商:ON Semiconductor 功能描述:PROGRAMMABLE PHASED-LOCKED-LOOP CLOCK GENERATOR, SSOP - Tape and Reel |
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