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參數(shù)資料
| 型號： | FS6377-01IG-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SOIC |
| 標準包裝： | 3,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
FS6377
6.2 Power-Down
All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is
asserted.
Table 4: Power-Down Bits
Name
Description
Power-Down PLL A
PDPLL_A
(Bit 21)
Bit = 0
Bit = 1
Power on
Power off
Power-Down PLL B
PDLL_B
(Bit 45)
Bit = 0
Bit = 1
Power on
Power off
Power-Down PLL C
PDLL_C
(Bit 69)
Bit = 0
Bit = 1
Power on
Power off
Reserved (0)
(Bit 69)
Set these reserved bits to zero (0)
Power-Down POST Divider A
PDPOSTA
(Bit 120)
Bit = 0
Bit = 1
Power on
Power off
Power-Down POST Divider B
PDPOSTB
(Bit 121)
Bit = 0
Bit = 1
Power on
Power off
Power-Down POST Divider C
PDPOSTC
(Bit 122)
Bit = 0
Bit = 1
Power on
Power off
Power-Down POST Divider D
PDPOSTD
(Bit 123)
Bit = 0
Bit = 1
Power on
Power off
Table 5: Divider Control Bits
Name
Description
REFDIV_A[7:0]
(Bits 7-0)
Reference Divider A (NR)
REFDIV_B[7:0]
(Bits 31-24)
Reference Divider B (NR)
REFDIV_C1[7:0]
(Bits 55-48)
Reference Divider C1 (NR)
selected when the SEL_CD pin = 0
REFDIV_C2[7:0]
(Bits 79-72)
Reference Divider C2 (NR)
selected when the SEL_CD pin = 1
Feedback Divider A (NF)
FBKDIV_A[10:0]
(Bits 18-8)
FBKDIV_A[2:0]
FBKDIV_A[10:3]
A-Counter value
M-Counter value
Feedback Divider B (NF)
FBKDIV_B[10:0]
(Bits 42-32)
FBKDIV_B[2:0]
FBKDIV_B[10:3]
A-Counter value
M-Counter value
Feedback Divider C1 (NF)
selected when the SEL_CD pin = 0
FBKDIV_C1[10:0]
(Bits 66-56)
FBKDIV_C1[2:0]
FBKDIV_C1[10:3]
A-Counter value
M-Counter value
Feedback Divider C2 (NF)
selected when the SEL_CD pin = 1
FBKDIV_C2[10:0]
(Bits 90-80)
FBKDIV_C2[2:0]
FBKDIV_C2[10:3]
A-Counter value
M-Counter value
Rev. 4 | Page 11 of 24 | www.onsemi.com
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