參數(shù)資料
型號(hào)： FS2540-9ERD0TB1
廠商： POWER-ONE INC
元件分類(lèi)： 電源模塊
英文描述： 2-OUTPUT DC-DC REG PWR SUPPLY MODULE
封裝： METAL, CASE S02, MODULE
文件頁(yè)數(shù)： 20/33頁(yè)
文件大?。?/td> 438K
代理商： FS2540-9ERD0TB1
S Series Data Sheet
100 Watt AC-DC and DC-DC Converters
APR 26, 2006 revised to SEP 25, 2006
Page 27 of 33
www.power-one.com
NPN output (D5 - DD):
Pin 20 (D) is internally connected via the collector-emitter
path of an NPN transistor to Vo1+ or Vo+. VD < 0.4 V
(logic low) corresponds to a monitored voltage level (Vi
and/or Vo1) > Vt +Vh. The current ID through pin 20
should not exceed 20 mA. This output is not protected
against external overvoltages. VD should not exceed 40 V.
Vi, Vo1 status
D output,
VD
Vi or Vo1 < Vt
high, H,
ID ≤ 25 A at VD = 40 V
Vi and Vo1 > Vt + Vh
low, L,
VD ≤ 0.4 V at ID = 20 mA
JFET output (D0 - D4):
Pin 20 (D) is internally connected via the drain-source path
of a JFET (self-conducting type) to Vo1+ or Vo+.
VD ≤ 0.4 V (logic low) corresponds to a monitored voltage
level (Vi and/or Vo1) < Vt. The current ID through the JFET
should not exceed 2.5 mA. The JFET is protected by a
0.5 W Zener diode of 8.2 V against external overvoltages.
Vi, Vo1 status
D output,
VD
Vi or Vo1 < Vt
low, L,
VD ≤ 0.4 V at ID = 2.5 mA
Vi and Vo1 > Vt + Vh
high, H,
ID ≤ 25 A at VD = 5.25 V
Fig. 31
Option D1 - D0: JFET output, ID ≤ 2.5 mA
Table 21: D-output logic signals
Version of D
Vi << Vt resp. Vo << Vt
Vi >> Vt + Vh resp. Vo >> Vt
Configuration
D1, D2, D3, D4, D0
low
high
JFET
D5, D6, D7, D8, D9, DD
high
low
NPN
Vo1+
Vo1–
D
VD
ID
Rp
Input
11007
Vo1+
Vo1–
D
VD
ID
Rp
Input
11006
Fig. 32
Option D5 - DD: NPN output, Vo1 ≤ 40 V, ID ≤ 20 mA
Threshold tolerances and hysteresis:
If Vi is monitored, the internal input voltage after the input
filter is measured. Consequently, this voltage differs from
the voltage at the connector pins by the voltage drop
ΔVti
across the input filter. The threshold levels of the D0 and
D9 options are factory-adjusted at nominal output current
Io nom and at TA = 25 °C. The value of ΔVti depends upon
the input voltage range (CS, DS, ..), threshold level Vt,
temperature and input current. The input current is a
function of the input voltage and the output power.
Fig. 33
Definition of Vti, ΔVt i and ΔVhi (JFET output)
ΔV
ti
Vhi
VD low
VD
VD high
Vi
P
o
=
P
o
nom
P
o
=
0
P
o
=
0
Vti
P
o
=
P
o
nom
11021
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