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參數(shù)資料
| 型號(hào)： | FPD87392BXBVQ |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
| 中文描述： | 3.3 TFT - LCD的雙LVDS輸入定時(shí)控制器/雙⑩輸出區(qū)特別職務(wù)隊(duì)的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下 |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 1980K |
| 代理商： | FPD87392BXBVQ |
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Input Signal Timing
Sync only mode, no DE inputted, is supported when the SYNC pin (Bonding Option pin) is enable high. Whenever DE signal is
inputted, it works as DE mode. In the DE mode, H-blank min is considered with Failure detection mode enabled. In the defaults
mode, T
valid_H
should be subtracted in the table below.
Graphic
Mode
Sync Mode (Bonding Option)
DE Mode
Number of
Total
Horizontal
Lines in a
Frame
Number of
Total Pixel
Clocks
in a
Horizontal
Line
H-Timing (clocks)
V-Timing (lines)
H-Timing
(clocks)
V-Timing
(lines)
From
Sync
to Data
Typ
248
128
304
Total H-Timing
From
Sync
to Data
Typ
38
12
46
Total V-Timing
H-Blank
H-Blank
Detection
Min
1430
1550
1804
Max
2047
2047
4095
Min
1066
1066
1250
Max
2047
2047
2047
Min
150
150
204
Min
2
2
2
Typ
1066
1066
1250
Typ
1688
1688
2160
SXGA
SXGA+
UXGA
Note:
H = Lines
Supports VESA Standard in SYNC Mode (B/O SYNC Pin = High)
SXGA
1280
48
112
248
1024
1
3
38
SXGA+
1400
48
112
128
1050
1
3
12
UXGA
1600
64
192
304
1200
1
3
46
Unit
clock
clock
clock
clock
Line
Line
Line
Line
Horizontal
WIDTH
HFP
HSW
HBP
HEIGHT
VFP
VSW
VBP
Vertical
20104317
FIGURE 17. Video Signal Format
F
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| FPD87392BXB | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
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