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參數(shù)資料
| 型號(hào)： | FPD87346VS |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
| 中文描述： | 低EMI，低動(dòng)態(tài)功耗（的SVGA）的XGA /英寸WXGA的TFT -低擺幅差分信號(hào)（RSDS⑩）產(chǎn)出LCD定時(shí)控制器 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 105K |
| 代理商： | FPD87346VS |
Block Diagram
Functional Description
FPD-LINK RECEIVER
The LVDS based FPD-Link Receiver inputs video data and
control timing through 4-LVDS channels plus clock to provide
24-bit color or 3-LVDS channels can be used for 18-bit color.
The video data is converted to a parallel data stream and
routed to the 8-6 bit translator.
SPREAD SPECTRUM SUPPORT
The FPD-Link receiver supports graphics controllers with
Spread Spectrum interfaces for reducing EMI. The Spread
Spectrum methods supported are Center and Down Spread.
A maximum of 2% total is supported at a frequency modu-
lation of 100kHz maximum.
8-6 BIT TRANSLATOR
8-bit data is reduced to a 6-bit data path via a time multi-
plexed dithering technique or simple truncation of the LSBs.
This function is enabled via the input control pins.
DATAPATH BLOCK AND RSDS TRANSMITTER
6(8)-bit video data (RGB) is input to the Datapath Block
supports up to an 85 MHz pixel rate. The data is delayed to
align the Column Driver Start Pulse (STH) with the Column
Driver data. The data bus (RSR[2:0]P/N, RSG[2:0]P/N,
RSB[2:0]P/N) outputs at a 170 MHz rate on 9 differential
output channels. The clock is output on the RSCKP/N differ-
ential pair. The RSDS Column Drivers latch data on both
positive and negative edges of the clock. The RSDS output
setup/hold
timings
are
also
RSDS[2:0] input pins.
adjustable
through
the
TIMING CONTROL FUNCTION
The Timing Control function generates control to Column
Drivers, Row Drivers, and power supply. The GPOs (General
Purpose Outputs) provide for CD latch pulse, REV, and Row
Driver control generation. The General Purpose Outputs
allow the user to generate control anywhere within the frame
data. Standard Row Driver interface or Custom Row Driver
interfaces can be implemented with the GPOs (General
Purpose Outputs).
RSDS OUTPUT VOLTAGE CONTROL
The RSDS output voltage swing is controlled through an
external load resistor connected to the R
pin. The RSDS
output signal levels can be adjusted to suit the particular
application. This is dependent on overall LCD module design
characteristics such as trace impedance, termination, etc.
The RSDS output voltage is inversely related to the R
PI
value. Lower R
values will increase the RSDS output volt-
age swing and consequently overall power consumption will
also increase.
20061519
FIGURE 2. Block Diagram
F
www.national.com
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FPD87352 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FPD87352CXA 3.3V TFT-LCD Timing Controller with Single LVDS Input/Dual RSDS Outputs Including RTC (Response Time Compensation) for TFT-LCD Monitors and TV (XGA/WXGA/HDTV I,II,-) |
| FPD87352CXA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V TFT-LCD Timing Controller with Single LVDS Input/Dual RSDS Outputs Including RTC for TFT-LCD Monitors and TV |
| FPD87352CXAVV | 制造商:Texas Instruments 功能描述:LVDS TIMING CONTROLLER SMD 87352 |
| FPD87352CXAVV/NOPB | 功能描述:IC TIMING CTLR TFT-LCD 176-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| FPD87370 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FPD87370AXA Low EMI, Low Dynamic Power VGA/XGA/WXGA TFT-LCD Timing Controllerwith Reduced Swing Differential Signaling (RSDS) Outputs |
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