- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370213 > FMS9875KGC100 PDF資料下載
參數(shù)資料
| 型號(hào)： | FMS9875KGC100 |
| 文件頁(yè)數(shù)： | 6/29頁(yè) |
| 文件大?。?/td> | 481K |
| 代理商： | FMS9875KGC100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)
PRODUCT SPECIFICATION
FMS9875
6
REV. 1.2.15 1/14/02
Register Definitions
PLL Control Register (01)
PHASE
7-0
0B
Sampling clock phase.
PHASE
4-0
stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments. Default value is decimal 16.
80
PLLCTRL
CONFIG 2
0C
0D
0E
0F
PLL Control.
Configuration Register No. 2.
Clamp Control Register.
Reserved.
24
00
00
00
Bit no.
1-0
Name
SUBDIV
1-0
Type
R/W
Description
PLL Subdivide ratio.
Selects the ratio of the divider following the PLL.
00:
divide-by 1
01:
divide-by 2
10:
divide-by 4
11:
reserved
2
PLLFAZ
R/W
PLL Sub-divider Phase.
Selects the phase of the divide-by-2 output.
(Invalid for other outputs)
Reserved.
PLL divide ratio, LSBs.
PLLN + 1 = total number of pixels per horizontal line.
3
–
R/W
R/W
7-4
PLLN
3-0
Configuration Register 1 (0A)
Bit no.
0
1
Name
Type
Description
XCKSEL
R/W
External Clock Select.
Select internal clock source.
0:
Internal PLL
1:
XCK input.
External Clamp Polarity.
Select clamp polarity.
0:
Active L.
1:
Active H.
External Clamp Select.
Select clamp source.
0:
Internally generated by PLL referenced to HSIN.
1:
External CLAMP input.
Coast Polarity.
Select COAST input polarity.
0:
Active L.
1:
Active H.
HSIN Polarity.
Select horizontal sync input polarity. PLL is locked to selected
edge:
0:
Falling edge.
1:
Rising edge.
1:
1:
2
XCLAMPOL
R/W
3
XCLAMP
R/W
4
COASTPOL
R/W
5
HSPOL
R/W
6
7
—
—
R
R
Name
Address
Function
Default (hex)
PHASE
4–0
X X X
SUBDIV
1–0
X X X X
PLLN
3–0
X X X
X
X X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FMS9875KGC100X | 1-Bit Bidirectional Voltage-Level Translator With Auto Direction Sensing and +/-15-kV ESD Protect 6-SOT -40 to 85 |
| FMS9875KGC140 | Integrated Photo Flash Charger and IGBT Driver 16-QFN -35 to 85 |
| FMS9875KGC140X | |
| FMS988AKAC100 | Signal Conditioner |
| FMS988AKAC140 | Signal Conditioner |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FMS9875KGC100X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| FMS9875KGC140 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| FMS9875KGC140X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| FMS9875KWC | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| FMS9884A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。