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參數(shù)資料
| 型號： | FMS7857MTDT |
| 英文描述： | Ten Distributed-Output Clock Driver |
| 中文描述： | 十分布式輸出時鐘驅(qū)動器 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 39K |
| 代理商： | FMS7857MTDT |
PRODUCT SPECIFICATION
FMS7857
2
REV. 0.0.5 6/19/00
A
Pin Assignments
Pin Description
Pin Name
GND
Pin #
Pin Type
PWR
Description
1, 7, 8, 18, 24, 25, 31,
41, 42, 48
4, 11, 12, 15, 21, 28,
34, 38, 45
3,5,10,20,22,27,29,3
9,44,46
2, 6, 9, 19, 23, 26, 30,
40, 43, 47
37
Ground Connection.
Connect all ground pins to the common
system ground plane.
Power Connection.
Power supply for all the outputs.
VDD
PWR
Q(0:9)
OUT
Clock Outputs.
Clock outputs 0:9 are buffer clocks of input.
Q(0:9)
OUT
Inverted Clock Outputs.
Clock outputs 0:9 are buffer clocks of
input.
Power Down.
When low, all outputs are in high impedance, and
PLL is shut off. Normal operation when asserted high.
Feedback Clock Output.
Dedicated pin for FBIN. For proper
operation, FBOUT/FBOUT must be connect of FBIN/FBIN,
respectively.
Feedback Clock Input.
PLL feedback input. The user connects
it to FBOUT to FBIN and FBOUT to FBIN.
Power Connection.
Power supply for PLL. Connect to 3.3V.
When low, PLL is bypassed and CLK/CLK is directly connect to
all the outputs. In this mode, the chip is a buffer.
Input Clock.
Input of PLL supplied by the user.
Analog Ground Connection.
Connect to common ground
plane.
PWRDWN
IN
FBOUT/
FBOUT
32, 33
OUT
FBIN/FBIN
36, 35
IN
AVDD
16
PWR
CLK/CLK
AGND
13, 14
17
IN
PWR
GND
Q0
Q0
VDD
Q1
Q1
FMS7857
48 TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
41
40
39
38
37
36
35
34
33
32
31
30
29
28
42
43
44
45
46
47
48
GND
Q2
Q2
GND
Q3
Q3
VDD
VDD
FBIN
FBIN
PWRDWN
VDD
Q7
Q7
Q5
Q5
Q6
Q6
GND
GND
VDD
CLK
CLK
VDD
AVDD
AGND
GND
25
27
26
VDD
Q4
Q4
GND
GND
GND
Q8
Q8
GND
VDD
Q9
VDD
FBOUT
FBOUT
Q9
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相關(guān)代理商/技術(shù)參數(shù) |
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| FMS7951 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Zero Delay Clock Multiplier |
| FMS7951KWC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FMS7951KWCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Nine Distributed-Output Clock Driver |
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