參數(shù)資料
型號(hào)： FMS7401LVN14
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： Digital Power Controller
中文描述： 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14
封裝： PLASTIC, DIP-14
文件頁(yè)數(shù)： 13/80頁(yè)
文件大小： 1535K
代理商： FMS7401LVN14
PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
13
3
Power Saving Modes
The FMS7401/7401L has both Halt and Idle power saving modes. Each mode is controlled by software and offers the advan-
tage of reducing the total current consumption of the device in an application. For all current consumption details, please refer
to the
Electrical Characteristics
section of the datasheet. In order to maintain proper Vcc voltage regulation of the FMS7401,
the internal regulator remains enabled—making the current consumption much higher than the FMS7401L for both Halt and
Idle Modes.
1
3.1
Halt Mode is a power saving feature that almost completely shuts down the device for current conservation. The device is
placed into Halt Mode by setting the Halt enable bit (EHALT) of the HALT register using either the “LD M, #” or the “SBIT #,
M” instructions in the software. EHALT is a write only bit and is automatically cleared upon exiting Halt Mode. When enter-
ing Halt Mode, the internal oscillator and all other on-chip systems including the Programmable Comparator (COMP) and
Brown-out Reset (BOR) circuits are shut down. For the FMS7401, to maintain proper Vcc voltage regulation, the internal reg-
ulator circuit remains enabled while in Halt Mode.
Halt Mode
The device can exit Halt Mode only by the Multi-input Wakeup (MIW) circuit.
2
Therefore, prior to entering Halt Mode, soft-
ware must first configure the MIW circuit. After a wakeup from Halt Mode, a T
HALT_REC
3
start-up delay is initiated to allow the
internal oscillator and other analog circuits to stabilize before normal device execution resumes. Immediately after exiting Halt
Mode, software must clear the Power Mode Clear (PMC) register by using only the “LD M, #” instruction (see
Figure 5
).
Table 4.
HALT Register Definition
Figure 5. Recommended Halt/Idle Flow
3.1.1 PLL Steps for Halt Mode
When using Halt Mode and the PLL in an application, software must take the appropriate steps in order to keep the integrity of
the clock structure before entering and after exiting Halt since the PLL must be disabled. While in Halt Mode, all other device
circuits except for the MIW are disabled. Once the PLL is disabled, all output frequencies are turned off. If the PLL is re-
HALT Register (addr. 0xB7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EIDLE
EHALT
Normal Mode
Halt Mode
Resume Normal
Mode
LD HALT, #01H
LD PMC, #00H
Multi-Input
Wakeup
Normal Mode
Idle Mode
Resume Normal
Mode
LD PMC, #00H
Timer 0
Overflow
Multi-Input
Wakeup
LD HALT, #02H
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