
FM8P51
Rev1.2 Mar 15, 2005
P.6/FM8P51
FEELING
TECHNOLOGY
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
In FM8P51 series, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank.
TABLE 1.1: Registers File Map for FM8P51 Series
Description
FSR<7:6>
Address
0 0
Bank 0
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
SPIRCB
SPITXB
SPISTAT
SPICON
TMR1
PR1
0 1
Bank 1
1 0
Bank 2
1 1
Bank 3
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
N/A
OPTION
IOSTA
IOSTB
IOSTC
IOSTD
IOSTE
T1CON
PHCON
PCON
INTEN
05h
06h
07h
08h
09h
Memory back to address in Bank 0
T23CON
TMR2
PR2
TMR3
PR3
PWMCON
PW0DCL
PW0DCH
PW1DCL
PW1DCH
RFCCON
RFCDL
RFCDH
CMPDX
CMPDY
CMPSTAT
0Ch
0Dh
0Eh
0Fh
10h
|
1Fh
General
Purpose
Registers
Memory back to address in Bank 0
20h
|
3Eh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
3Fh
INTFLAG
Memory back to address in Bank 0
TABLE 1.2: The Registers Controlled by OPTION/OPTIONR or IOST/IOSTR Instructions
Address
Name
B7
B6
Unbanked
N/A (r/w)
OPTION
/PHBCE
GIE
05h (r/w)
IOSTA
06h (r/w)
IOSTB
07h (r/w)
IOSTC
08h (r/w)
IOSTD
09h (r/w)
IOSTE
0Ch (r/w)
T1CON
0Dh (r/w)
PHCON
HDC
0Eh (r/w)
PCON
LVDTE
ODE
0Fh (r/w)
INTEN
SPITXIE
RFCIE
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’.
B5
B4
B3
B2
B1
B0
PSA
PS2
PS1
PS0
Port A I/O Control Register
Port B I/O Control Register
Port C I/O Control Register
Port D I/O Control Register
Port E I/O Control Register
WDTE
-
T3IE
T2IE
T1ON
/PHD
-
SPIRCIE
T1P1
/PHB
-
INTIE
T1P0
/PHA
/WUE
T0IE
/PHE
ROC
T1IE