
10
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FM75 Rev. A.4
Reading
If the pointer is already pointing to the desired register, the master
can read from that register by setting the read/write bit (following
the slave address) to a 1. After sending an ACK, the FM75 will
begin transmitting data during the following clock cycle. If the
Configuration Register is being read, the FM75 will transmit one
byte of data (see Figure 10). The master device should respond
with a NACK followed by a stop condition. If the Temperature, T
OS
or T
Register is being read, the FM75 will transmit two bytes
of data (see Figure 9). The master must respond to the first byte
of data with an ACK and to the second byte of data with a NACK
followed by a stop condition.
To read from a register other than the one currently being pointed
to by the Command Register, a pointer set to the desired register
must be done as described previously. Immediately following the
pointer set, the master must perform a repeat start condition (see
Figures 8 and 12) which indicates to the FM75 that a new
operation is about to occur. It is important to note that if the repeat
start condition does not occur, the FM75 will assume that a write
is taking place, and the selected register will be overwritten by the
upcoming data on the data bus. After the start condition, the
master must again send the device address and read/write bit.
This time the read/write bit must be set to 1 to indicate a read. The
rest of the read cycle is the same as described in the previous
paragraph for reading from a preset pointer location.
Writing
All writes must be proceeded by a pointer set as described
previously, even if the pointer is already pointing to the desired
register.
Immediately following the pointer set, the master must begin
transmitting the data to be written. If the master is writing to the
Configuration Register, one byte of data must be sent (see Figure
13). If the T
or T
Register is being written to, the master must
send two bytes of data (see Figure 11). After transmitting each
byte of data, the master must release the SDA line for one clock
to allow the FM75 to acknowledge receiving the byte. The write
operation should be terminated by a stop signal from the master.
Inadvertent 8-Bit Read from a 16-Bit
Register: A Caution
An inadvertent 8-bit read from a 16-bit register, with the D7 bit low,
can cause the FM75 to pause in a state where the SDA line is
pulled low by the output data and is incapable of receiving either
a stop or a start condition from the master. The only way to remove
the FM75 from this state is to continue clocking for 9 cycles until
SDA goes high, at which time issuing a stop condition will reset the
FM75. This sequence can be seen in Figure 7 below.
D7 D6 D5 D4 D3 D2 D1 D0
D7
Address Byte
Most Significant
Data Byte
(from FM75)
1
0
0
1
A2 A1 A0R/W
Master must
detect error
condition on
FM75
A
N
Nine additional clock cycles to reset the FM75
Ack
from
FM75
No Ack
from
Master
No Ack
from
Master
Start
from
Master
SCL
SDA
Stop intended by
Master, but FM75
SDA line locked
low
D6 D5 D4 D3 D2 D1 D0 N
Stop
Condition
from
Master
Figure 7. Inadvertent 8-Bit Read from 16-Bit Register Where D7 = 0 and Forces Output Low