參數(shù)資料
型號: FM3264
廠商: Electronic Theatre Controls, Inc.
英文描述: Integrated Processor Companion with Memory
中文描述: 綜合處理器與記憶體伴侶
文件頁數(shù): 13/20頁
文件大?。?/td> 285K
代理商: FM3264
or Stop condition prior to the 8
th
data bit. The figures
below illustrate a single- and multiple-writes to
FM3204/16/64/256
Rev 2.1
Dec. 2004
Page 13 of 20
memory.
Figure 10. Single Byte Memory Write
Figure 11. Multiple Byte Memory Write
Memory Read Operation
There are two types of memory read operations. They
are current address read and selective address read. In
a current address read, the FM32xx uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to first set the
address to a specific value.
Current Address & Sequential Read
As mentioned above the FM32xx uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the FM32xx
will begin shifting data out from the current address
on the next clock. The current address is the value
held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte,
this indicates that the FM32xx should read out
the next sequential byte.
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM32xx attempts to
read out additional data onto the bus. The four valid
methods follow.
1.
The bus master issues a NACK in the 9
th
clock
cycle and a Stop in the 10
th
clock cycle. This is
illustrated in the diagrams below and is
preferred.
2.
The bus master issues a NACK in the 9
th
clock
cycle and a Start in the 10
th
.
3.
The bus master issues a Stop in the 9
th
clock
cycle.
4.
The bus master issues a Start in the 9
th
clock
cycle.
If the internal address reaches the top of memory, it
will wrap around to 0000h on the next read cycle.
The figures below show the proper operation for
current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM32xx
Start
Address & Data
Stop
Acknowledge
Address LSB
A
Data Byte
A
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM32xx
Start
Address & Data
Stop
Acknowledge
Address LSB
A
相關PDF資料
PDF描述
FM3264-G Integrated Processor Companion with Memory
FM3264-S Integrated Processor Companion with Memory
FM34W02ULZ RoHS Compliant:Yes RoHS Compliant: Yes
FM34W02UEM8 I2C Serial EEPROM
FM34W02UEMT8 I2C Serial EEPROM
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