參數(shù)資料
型號(hào)： FM3264-S
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Processor Companion with Memory
中文描述： 綜合處理器與記憶體伴侶
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 285K
代理商： FM3264-S
FM3204/16/64/256
Rev 2.1
Dec. 2004
Page 9 of 20
0Ch
Event Counter Control
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
RC
CC
C2P
C1P
RC
Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by
C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of
Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is
“don’t care” when CC=1. Battery-backed, read/write.
CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P is “don’t care” when CC=1. The value
of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write.
CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. The value of Event Counter 1 may
inadvertently increment if C1P is changed. Battery-backed, read/write.
Companion Control
D7
D6
D5
D4
CC
C2P
C1P
0Bh
D3
D2
D1
D0
SNL
-
-
WP1
WP0
VBC
VTP1
VTP0
SNL
Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only.
SNL cannot be
cleared once set to 1.
Nonvolatile, read/write.
Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write.
Write protect addresses
WP1
WP0
None
0
0
Bottom 1/4
0
1
Bottom 1/2
1
0
Full array
1
1
VBAK Charger Control. Setting VBC to 1 causes a 15 μA trickle charge current to be supplied on VBAK.
Clearing VBC to 0 disables the charge current. Nonvolatile, read/write.
VTP select. These bits control the reset trip point for the low V
DD
reset function. Nonvolatile, read/write.
VTP
VTP1
VTP0
2.6V
0
0
2.9V
0
1
3.9V
1
0
4.4V
1
1
Watchdog Control
D7
D6
D5
D4
WP1-0
VBC
VTP1-0
0Ah
D3
D2
D1
D0
WDE
Watchdog Enable. When WDE=1 the watchdog timer can cause the /RST signal to go active. When WDE = 0 the
timer runs but has no effect on /RST. Note as the timer is free-running, users should restart the timer using WR3-0
prior to setting WDE=1. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write.
Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog
timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write.
Watchdog timeout
WDT4 WDT3 WDT2 WDT1 WDT0
Invalid – default 100 ms
0
0
100 ms
0
0
200 ms
0
0
300 ms
0
0
.
.
.
2000 ms
1
0
2100 ms
1
0
2200 ms
1
0
.
.
.
2900 ms
1
1
3000 ms
1
1
Disable counter
1
1
-
-
WDT4
WDT3
WDT2
WDT1
WDT0
WDE
WDT4-0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
1
0
1
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