參數(shù)資料
型號: FM27C256Q150
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 262,144-Bit (32K x 8) High Performance CMOS EPROM
中文描述: 32K X 8 UVPROM, 150 ns, CDIP28
封裝: WINDOWED, CERDIP-28
文件頁數(shù): 4/10頁
文件大?。?/td> 103K
代理商: FM27C256Q150
4
www.fairchildsemi.com
F
FM27C256
AC Test Conditions
Output Load
1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times
5 ns
Input Pulse Levels
0.45 to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs
Outputs
0.8V and 2.0V
0.8V and 2.0V
AC Waveforms
(Note 6) (Note 7) (Note 9)
Note 1:
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
and t
compare level is determined as follows:
High to TRI-STATE
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE.
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
μ
F ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
TTL Gate: I
= 1.6 mA, I
= -400
μ
A.
C
L
= 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11:
CMOS inputs: V
IL
= GND
±
0.3V, V
IH
= V
CC
±
0.3V.
ADDRESSES VALID
VALID OUTPUT
Hi-Z
Hi-Z
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
ADDRESSES
CE
OE
OUTPUT
t
OE
(Note 3)
t
(NACC
t
CE
t
CE
(Notes 4, 5)
t
OH
t
(Notes 4, 5)
DS800034-4
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