參數(shù)資料
型號: FM25C041UV
廠商: Fairchild Semiconductor Corporation
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內256個8位每字舉辦的串行CMOS
文件頁數(shù): 3/11頁
文件大?。?/td> 103K
代理商: FM25C041UV
3
www.fairchildsemi.com
FM25C041U Rev. B
F
Standard Voltage 4.5
V
CC
5.5V Specifications
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
-65
°
C to +150
°
C
All Input or Output Voltage with
Respect to Ground
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300
°
C
ESD Rating
DC and AC Electrical Characteristics
4.5V
V
CC
5.5V (unless otherwise specified)
Symbol
Parameter
2000V
Operating Conditions
Ambient Operating Temperature
FM25C041U
FM25C041UE
FM25C041UV
0
°
C to +70
°
C
-40
°
C to +85
°
C
-40
°
C to +125
°
C
Power Supply (V
CC
)
4.5V to 5.5V
Conditions
Min
Max
Units
I
CC
I
CCSB
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
OP
t
RI
t
FI
t
CLH
t
CLL
t
CSH
t
CSS
t
DIS
t
HDS
t
CSN
t
DIN
t
HDN
t
PD
t
DH
t
LZ
t
DF
t
HZ
t
WP
Operating Current
/CS = V
IL
/CS = V
CC
V
IN
= 0 to V
CC
V
OUT
= GND to V
CC
3
mA
μ
A
μ
A
μ
A
V
Standby Current
50
Input Leakage
-1
+1
Output Leakage
-1
+1
CMOS Input Low Voltage
-0.3
V
CC
* 0.3
V
CC
+ 0.3
0.4
CMOS Input High Voltage
0.7 * V
CC
V
Output Low Voltage
I
OL
= 1.6 mA
I
OH
= -0.8 mA
V
Output High Voltage
V
CC
- 0.8
V
SCK Frequency
2.1
MHz
μ
s
μ
s
ns
Input Rise Time
2.0
Input Fall Time
2.0
Clock High Time
(Note 2)
190
Clock Low Time
(Note 2)
190
ns
Min /CS High Time
(Note 3)
240
ns
/CS Setup Time
240
ns
Data Setup Time
100
ns
/HOLD Setup Time
90
ns
/CS Hold Time
240
ns
Data Hold Time
100
ns
/HOLD Hold Time
90
ns
Output Delay
C
L
= 200 pF
240
ns
Output Hold Time
0
ns
/HOLD to Output Low Z
100
ns
Output Disable Time
C
L
= 200 pF
240
ns
/HOLD to Output High Z
100
ns
Write Cycle Time
1
16 Bytes
10
ms
Capacitance
T
A
= 25
°
C, f = 2.1/1 MHz (Note 4)
Symbol
Test
Typ Max Units
C
OUT
Output Capacitance
3
8
pF
C
IN
Input Capacitance
2
6
pF
AC Test Conditions
Output Load
C
L
= 200 pF
Input Pulse Levels
0.1 * V
CC
0.9 * V
CC
Timing Measurement Reference Level
0.3 * V
CC
- 0.7 * V
CC
Note 1:
Stress above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2:
The f
OP
frequency specification specifies a minimum clock period of 1/f
. Therefore, for every f
clock cycle, t
+ t
must be equal to or greater than 1/f
OP
. For
example, for a f
OP
of 2.1MHz, the period equals 476ns. In this case if t C
LH
= is set to 190ns, then t
CLL
must be set to a minimum of 286ns.
Note 3:
/CS must be brought high for a minimum of t
CSH
between consecutive instruction cycles.
Note 4:
This parameter is periodically sampled and not 100% tested.
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