參數(shù)資料
型號: FIN1532M
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 5V LVDS 4-Bit High Speed Differential Receiver
中文描述: QUAD LINE RECEIVER, PDSO16
封裝: 0.150 INCH, MS-012, SOIC-16
文件頁數(shù): 3/6頁
文件大?。?/td> 246K
代理商: FIN1532M
3
www.fairchildsemi.com
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3:
All typical values are at T
A
=
25
°
C and with V
CC
=
5V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
Criteria: Input t
R
=
t
F
<
1 ns, V
ID
=
300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, V
OL
<
0.5V, V
OH
>
2.4V.
All channels switching in phase.
Note A:
All input pulses have frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note B:
C
L
includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
t
PLH
Propagation Delay
LOW-to-HIGH
1.0
2.0
3.0
ns
t
PHL
Propagation Delay
HIGH-to-LOW
Output Rise Time (20% to 80%)
1.0
2.0
3.0
ns
|V
ID
|
=
400 mV, C
L
=
10 pF, R
L
=
1k
See Figure 1 and Figure 2
t
TLH
t
THL
t
SK(P)
t
SK(LH)
,
t
SK(HL)
t
SK(PP)
f
MAX
1.3
ns
Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
1.1
0.2
ns
ns
0.5
0.1
0.3
ns
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Operating Frequency
1.0
ns
R
L
=
1k
, C
L
=
10 pF,
See Figure 1 and Figure 2
200
260
MHz
(Note 6)
LVTTL Output Enable Time from Z to HIGH R
L
=
1k
, C
L
=
10 pF,
LVTTL Output Enable Time from Z to LOW
t
ZH
t
ZL
t
HZ
t
LZ
8
8
12.0
12.0
ns
ns
See Figure 3 and Figure 4
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
4
4
8.0
8.0
ns
ns
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