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參數(shù)資料
| 型號(hào)： | FIN1048 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver |
| 中文描述： | 3.3 LVDS的4位流通過(guò)高速差分接收器 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 249K |
| 代理商： | FIN1048 |
3
www.fairchildsemi.com
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3:
All typical values are at T
A
=
25
°
C and with V
CC
=
3.3V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
Criteria: Input t
R
= t
F
<
1 ns, V
ID
=
300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, V
OL
<
0.5V, V
OH
>
2.4V.
All channels switching in phase.
Note A:
All differential input pulses have frequency
=
10MHz, t
R
or t
F
=
1ns
Note B:
C
L
includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(LH)
t
SK(HL)
t
SK(PP)
f
MAX
Propagation Delay LOW-to-HIGH
Propagation Delay HIGH-to-LOW
1.0
1.0
2.5
2.5
ns
ns
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
|V
ID
|
=
400 mV, C
L
=
10 pF,
R
L
=
1k
See Figure 1 and Figure 2
0.7
0.7
1.2
1.2
0.4
ns
ns
ns
0.3
ns
1.0
ns
Maximum Operating Frequency
(Note 6)
LVTTL Output Enable Time from Z to HIGH
R
L
=
1k
, C
L
=
10 pF,
see Figure 1 and Figure 2
200
375
MHz
t
ZH
t
ZL
t
HZ
t
LZ
6.0
ns
LVTTL Output Enable Time from Z to LOW
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
R
L
=
1k
, C
L
=
10 pF,
See Figure 3
6.0
6.0
6.0
ns
ns
ns
Applied Voltages (V)
Resulting Differential Input
Voltage (mA)
V
ID
100
100
100
100
100
100
600
600
600
600
600
600
Resulting Common Mode Input
Voltage (V)
V
IC
1.2
V
IA
1.25
V
IB
1.15
1.15
2.4
2.3
1.25
2.3
2.4
1.2
2.35
2.35
0.1
0
1.5
0
0.05
0.05
1.2
0.1
0.9
0.9
2.4
1.8
1.5
1.8
2.4
1.2
2.1
2.1
0.6
0
0
0.3
0.3
0.6
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