參數資料
型號: FIN1022MX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 運動控制電子
英文描述: TELECOM SWITCHING CIRCUIT|SOP|16PIN|PLASTIC
中文描述: 2-CHANNEL, CROSS POINT SWITCH, PDSO16
封裝: 0.150 INCH, MS-012, SOIC-16
文件頁數: 4/10頁
文件大小: 547K
代理商: FIN1022MX
www.fairchildsemi.com
4
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 4:
All typical values are at T
A
=
25
°
C and with V
CC
=
3.3V.
Note 5:
Part-to-part skew is the maximum delay time difference on like edges (LOW-to-HIGH or HIGH-to-LOW) for the same V
CC
and temperature condi-
tions.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 4)
t
PLHD
Differential Output Propagation Delay
LOW-to-HIGH
0.7
1.0
1.6
1.3
ns
R
L
=
75
, C
L
=
5 pF,
V
CC
=
3.3V, T
A
=
25
°
C
See Figure 4 and Figure 5
1.2
t
PHLD
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%)
0.7
1.0
290
1.6
1.3
580
ns
1.2
t
TLHD
t
THLD
t
PLH
ps
Differential Output Fall Time (80% to 20%)
Selection Propagation Delay
LOW-to-HIGH (SEL
n
to OUT
n
)
Selection Propagation Delay
HIGH-to-LOW (SEL
n
to OUT
n
)
Differential Output Enable Time
290
0.6
0.9
580
1.5
1.2
ps
ns
R
L
=
75
, C
L
=
5 pF,
V
CC
=
3.3V, T
A
=
25
°
C
See Figure 6 and Figure 7
1.1
t
PHL
0.6
0.9
1.5
1.2
ns
1.1
t
ZHD
3.5
ns
from Z-to-HIGH
Differential Output Enable Time
from Z-to-LOW
t
ZLD
3.5
ns
R
L
=
75
, C
L
=
5 pF
See Figure 8 and Figure 9
t
HZD
Differential Output Disable Time
from HIGH-to-Z
Differential Output Disable Time
3.5
ns
t
LZD
3.5
ns
from LOW-to-Z
Input (IN
n
+
/IN
n
) Setup Time to SEL
n
Input (IN
n
+
/IN
n
) Hold Time to SEL
n
Output Peak-to-Peak Jitter
t
SET
t
HOLD
t
JIT
See Figure 10
See Figure 10
2
23
1 PRBS Sequence at 800 Mbps
50% Duty Cycle at 800 Mbps
R
L
=
75
, C
L
=
5 pF, See Figure 4
0.5
0.5
0.3
0.3
ns
ns
190
35
ps
ps
20
900
f
TOG
t
SKEW
Maximum Toggle Frequency
800
Mbps
Within Device Channel-to-Channel Skew
Pulse Skew |t
PLHD
-t
PHLD
|
Part-to-Part Skew (Note 5)
35
0
100
80
225
500
ps
ps
ps
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