參數(shù)資料
型號(hào): FI1216MK2
廠商: NXP Semiconductors N.V.
英文描述: Desktop video tuner system CCIR B/G
中文描述: 桌面視頻調(diào)諧系統(tǒng)無線電咨詢委員會(huì)乙/克
文件頁數(shù): 14/24頁
文件大?。?/td> 148K
代理商: FI1216MK2
1996 Jul 09
14
Philips Components
Preliminary specification
Desktop video tuner
multi system CCIR L/L’ and B/G
FI1216MF MK2
APPLICATION INFORMATION
A detailed description of the I
2
C-bus specification, with applications, is given in brochure ‘‘The I
2
C-bus and how to
use it’’. This brochure may be ordered using the code number 9398 393 40011.
WRITE mode
Note
1.
A = Acknowledge.
A
DDRESS SELECTION
V
S
= +5 V (PLL supply voltage)
Note
1.
If the AS pin is left floating, the internal bias will automatically set the address to C2.
P
ROGRAMMABLE DIVIDER SETTINGS
(
BYTES
1
AND
2)
Divider ratio:
N = 16
× {
f
RF(pc)
+ f
IF(pc)
}, where (pc) is picture carrier and f
RF
and f
IF
are expressed in MHz
f
osc
=
N
16
(MHz).
N = (8192
×
n13) + (4096
×
n12) + (2048
×
n11) + (1024
×
n10) + (512
×
n9) + (256
×
n8) + (128
×
n7) + (64
×
n6) +
(32
×
n5) + (16
×
n4) + (8
×
n3) + (4
×
n2) + (2
×
n1) + n0
C
ONTROL BYTE
Charge pump settings:
CP = 1, for fast tuning
CP = 0, for moderate speed tuning with slightly better residual oscillator FM.
Test mode settings:
T2 = T1 = 0; T0 = 1, for normal operation.
PLL disabling:
OS = 0, for normal operation
OS = 1, for switching the charge pump to the high impedance state.
BYTE
BITS
7
MSB
1
0
n7
1
P7
6
5
4
3
2
1
0
LSB
0
n8
n0
OS
P0
A
(1)
Address byte
Program divider byte 1
Program divider byte 2
Control information byte 1
Control information byte 2
1
0
0
0
MA1
n10
n2
RSA
P2
MA0
n9
n1
RSB
P1
A
A
A
A
A
n14
n6
CP
P6
n13
n5
T2
P5
n12
n4
T1
P4
n11
n3
T0
P3
MA1
0
0
1
1
MA0
0
1
0
1
ADDRESS
C0
C2
C4
C6
VOLTAGE AT PIN 15
(see note 1)
0 to 0.1V
S
0.2 to 0.3V
S
0.4 to 0.6V
S
0.9V
S
to V
S
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