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參數(shù)資料
| 型號： | FEDS82V48540-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 393,216-Word 】 32-Bit 】 4-Bank FIFO-SGRAM |
| 中文描述： | 393216詞】32位】4銀行先進(jìn)先出，SGRAM |
| 文件頁數(shù)： | 4/44頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | FEDS82V48540-01 |
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FEDS82V48540-01
OKI Semiconductor
PIN DESCRIPTION
CLK
MS82V48540
4/44
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 – RA10
Column address: CA0 – CA7
Selects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
BA0 = “L”, BA1 = “L”: Bank A
BA0 = “H”, BA1 = “L”: Bank B
BA0 = “L”, BA1 = “H”: Bank C
BA0 = “H”, BA1 = “H”: Bank D
CS
CKE
Address
BA0, BA1
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
DQM0 –
DQM3
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and
DQM3 controls DQ24 to DQ31.
DQ0 – DQ31 Data inputs/outputs are multiplexed on the same pin.
*Notes: 1. When
CS
is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE,
DQM0, DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by BA0 and BA1.
BA0
BA1
Active, read or write
0
0
Bank A
1
0
Bank B
0
1
Bank C
1
1
Bank D
3. The auto precharge function is enabled or disabled by the A10/AP input when the read or
write command is issued.
A10/AP
BA0
BA1
0
0
0
After the end of burst, bank A holds the active status.
1
0
0
After the end of burst, bank A is precharged automatically.
0
1
0
After the end of burst, bank B holds the active status.
1
1
0
After the end of burst, bank B is precharged automatically.
0
0
1
After the end of burst, bank C holds the active status.
1
0
1
After the end of burst, bank C is precharged automatically.
0
1
1
After the end of burst, bank D holds the active status.
1
1
1
After the end of burst, bank D is precharged automatically.
Operation
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