參數(shù)資料
型號(hào)： FCPH100125-10
元件分類(lèi)： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 1250 MHz, QCC16
封裝： ROHS COMPLIANT PACKAGE-16
文件頁(yè)數(shù)： 1/8頁(yè)
文件大?。?/td> 527K
代理商： FCPH100125-10
SELECTABLE FREQUENCY SYNTHESIZER
SURFACE MOUNT MODEL: FCPH100125-10
1000 - 1250 MHz
optimized bandwidth
This product is manufactured under one or more of the following patents. Approved: 5,160,810; 5,122,621; 5,390,349; 5,416,449; 5,650,754; 5,805,431; 6,525,623; 6,850,575;
7,088,189; 7,180,381; 7,196,591; 7,262,670; 7,265,642; 7,292,113; 7,365,612; 7,495,525; 2,548,311; 2,548,317; 7,545,229; 7,580,693; 7,586,381; 7,605,670; 7,636,021; 2,533,623
| Pending: 60/493075; 60/501371 & 60/501790; 60/527957 & 60/528670; 60/563481; 60/564173; 60/589090; 60/601823; 60/605791; EV31369834; 11/259766; 60/622485 &
60/710310; 10/937525/60/736901; 60/732787; 7,495,525; 2,548,311; 2,548,317; 7,545,229; 2,563,174; 7,580,693; 7,612,296; 2,524,751
Copyright Synergy Microwave Corporation
201 McLean Boulevard Paterson, New Jersey 07504 USA Tel: (973) 881-8800 Fax: (973) 881-8361
E-Mail: sales@synergymwave.com World Wide Web: http://www.synergymwave.com
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FEATURES:
exceptionally Low phase noise
no programming Required
Lead Free - RohS Compliant
patented ReL-pRo technology
Small Size, Surface mount
buffered output
phase noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
100
1000
10000
100000
1000000
10000000
Offset Frequency (Hz)
Ph
ase
N
oi
se
(
dBc/
H
z)
1000 MHz
1100 MHz
1250 MHz
SPECIFICATIONS (Rev. G 12/23/10)
Frequency
1000 - 1250 MHz
Reference input Frequency
10 MHz
Reference input Voltage
1.0 V p-p to 3.3 V p-p
bias Voltage
Vcc
V (Vdc)
I (mA Max.)
digital
+5
15
tune
+5
10
VCo
+5
55
Lock detect indicator
CMOS 3.3 V
output power
+5 dBm (Min.)
Spurious Suppression
80 dB (Typ.)
harmonic Suppression
15 dB (Typ.)
power Up time
90 mSec (Typ.) 1
output impedance
50 Ohms (Nom.)
typical phase noise
Offset
Phase Noise
@ 10 kHz
-100 dBc/Hz
@ 100 kHz
-112 dBc/Hz
operating temperature Range -40 to +85 °C
1
From stable power on to stable lock detect.
Binary Frequency Selection Table
D3*
D2*
D1*
D0*
Freq. (MHz)
0
1000
0
1
1030
0
1
0
1045
0
1
1050
0
1
0
1065
0
1
0
1
1070
0
1
0
1095
0
1
1100
1
0
1175
1
0
1
1190
1
0
1
0
1195
1
0
1
1205
1
0
1210
1
0
1
1225
1
0
1245
1
1250
* Voltage levels: 0V or gnd. / +5V or open.
Absolute Maximum Ratings
Storage temp. Range
-55 to +125 C
bias Voltage (digital)
+5.25 V
bias Voltage (tune)
+28 V
bias Voltage (VCo)
+5.5 V
dC Voltage applied to RF out
± 25 V
相關(guān)PDF資料
PDF描述
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