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參數(shù)資料
| 型號： | FC80960HD80SL2LZ |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 16/102頁 |
| 文件大?。?/td> | 828K |
| 代理商： | FC80960HD80SL2LZ |
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80960HA/HD/HT
10
Advance Information
Datasheet
HOLD
I
S(L)
HOLD REQUEST
signals that an external agent requests access to the
processor’s address, data, and control buses. When HOLD is asserted, the
processor:
Completes the current bus request.
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and control pins.
HOLDA
O
H(1)
B(0)
R(Q)
HOLD ACKNOWLEDGE
indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
the HOLDA state while the RESET pin is asserted.
HOLDA is never granted while LOCK is asserted.
BOFF
I
S(L)
BUS BACKOFF
forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY/BTERM is enabled and:
When BOFF is asserted, the address, data, and control buses are floated on the
next clock cycle and the current access is aborted.
When BOFF is deasserted, the processor resumes by regenerating the aborted
bus access.
See
Figure 16 on page 40
for BOFF timing requirements.
BREQ
O
H(Q)
B(Q)
R(0)
BUS REQUEST
indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
processor stall status. BREQ can be used with BSTALL to indicate to an external
bus arbiter the processor’s bus ownership requirements.
BSTALL
O
H(Q)
B(Q)
R(0)
BUS STALL
indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
regain bus ownership to continue processing (i.e., it can no longer execute strictly
out of on-chip cache memory).
CT3:0
O
H(Z)
B(Z)
R(Z)
CYCLE TYPE
indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
Cycle Type
Program-initiated access using 8-bit bus
Program-initiated access using 16-bit bus
Program-initiated access using 32-bit bus
Event-initiated access using 8-bit bus
Event-initiated access using 16-bit bus
Event-initiated access using 32-bit bus
Reserved
Reserved for future products
Reserved
ADSCT3:0
00000
00001
00010
00100
00101
00110
00X11
01XXX
1XXXX
XINT7:0
I
A(E)
A(L)
EXTERNAL INTERRUPT
pins are used to request interrupt service. These pins
can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs can be programmed to be level (low or high) or edge (rising or falling)
sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are level sensitive in this mode.
Mixed Mode:The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act
as the five most significant bits of a vectored source. The least significant bits of
the vectored source are set to “010” internally.
NMI
I
A(E)
NON-MASKABLE INTERRUPT
causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source. NMI is falling edge triggered.
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FC80960HT60SL2G2 | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HT75SL2GT | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HA25SL2GU | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HA40SL2GW | CAP CER 3300PF 250V 10% X7R 0805 |
| FC80960HA33SL2GV | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FC80960HT60SL2G2 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HT75 S L2GT | 制造商:Intel 功能描述:MPU i960? Processor RISC 32-Bit 75MHz 208-Pin PQFP |
| FC80960HT75SL2GT | 功能描述:IC MPU I960HT 3V 75MHZ 208-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應商設備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| FC80B | 制造商:Datak Corporation 功能描述: |
| FC81 | 制造商:Datak Corporation 功能描述:Conn Type F Crimp ST Cable Mount Nickel |
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