參數(shù)資料
型號(hào)： FC80960HA25SL2GU
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
中文描述： 32-BIT, 25 MHz, RISC PROCESSOR, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 102/102頁(yè)
文件大?。?/td> 828K
代理商： FC80960HA25SL2GU
80960HA/HD/HT
96
Advance Information
Datasheet
Table 26. Data Sheet Version -006 to -007 Revision History
Section
Description
Entire data sheet
Formatted in new template.
“32-Bit Parallel Architecture” on page 1
Revised “1.2 Gbyte Internal Bandwith (75 MHz) to
“1.28 Gbyte ... (80 MHz)”.
Copyright Page
Updated legal text.
Section 3.0, “Package Information” on page 6
Added paaragraph two and
Table 5
.
Table 7 “80960Hx Processor Family Pin Descriptions”
on page 8
Corrected minor typeset and spacing errors.
BREQ
; Revised description.
ONCE
; last sentence, changed “l(fā)ow” to “high”.
TDI
and
TMS
; removed last sentence, “Pull this pin
low when not in use.”
Figure 2 “80960Hx 168-Pin PGA Pinout — View from
Top (Pins Facing Down)” on page 12
Added insert package marking diagram.
Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 18
Added insert package marking diagram.
Table 10 “80960Hx PQ4 Pinout — Signal Name
Order” on page 19
Corrected
TDO
(“O” was zero) and revised
alphabetical ordering.
Table 11 “80960Hx PQ4 Pinout — Pin Number Order”
on page 21
Corrected
TDO
(“O” was zero) and revised
alphabetical ordering.
Section 4.1, “Absolute Maximum Ratings” on page 29
Revised “V
CC
” to “VCC5” for “Voltage on Other Pins
...”.
Section 4.5, “VCCPLL Pin Requirements” on page 31
Added section.
Table 21 “80960Hx DC Characteristics” on page 32
Added footnote (1) to “I
LO
” notes column for “TDO”
pin.
Added footnote (10) to “C
IN
, C
OUT
and C
I/O
” pin.
Table 22 “80960Hx AC Characteristics” on page 34
Added overbars where required.
Modified “T
DVNH
” to list separate specifications for 3.3
V and 5 V.
Modified “T
, T
and T
” to reflect specific
80960HA, 80960HD and 80960HT values.
Figure 23 “I
CC
Active (Power Supply) vs. Frequency”
on page 43
Changed “5” to “0” on “CLKIN Frequency” axis.
Figure 49 “BREQ and BSTALL Operation” on page 66
Added figure and following text.
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