參數(shù)資料
型號: FB2031
廠商: NXP Semiconductors N.V.
英文描述: 9-bit latched/registered/pass-thru Futurebus transceiver
中文描述: 9位鎖存/注冊/直通Futurebus收發(fā)器
文件頁數(shù): 11/18頁
文件大?。?/td> 187K
代理商: FB2031
Philips Semiconductors
Product specification
FB2031
9-bit latched/registered/pass-thru Futurebus+ transceiver
1995 May 25
11
AC ELECTRICAL CHARACTERISTICS
(Commercial)
A PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C, V
= 5V,
L
= 50pF, R
L
= 500
MIN
TYP
120
150
2.5
2.4
4.2
2.9
2.8
4.3
2.6
2.4
4.7
1.5
1.7
3.9
2.1
2.0
3.8
1.9
1.7
3.2
T
amb
= 0 to +70
°
C,
= 5V
±
10%,
C
L
= 50pF, R
L
= 500
MIN
100
2.3
2.4
2.7
2.5
2.0
2.0
1.2
1.5
1.8
1.7
1.6
1.5
2.0
1.0
UNIT
MAX
MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
TLH
t
THL
Maximum clock frequency
Propagation delay (thru mode)
Bn to An
Propagation delay (transparent latch)
Bn to An
Propagation delay
LCBA to An
Propagation delay
SEL0 or SEL1 to An
Output enable time from High or Low
OEA to An
Output disable time to High or Low
OEA to An
Output transition time, An Port
10% to 90%, 90% to 10%
Output to output skew for multiple
channels
1
Pulse skew
2
t
PHL
– t
PLH
MAX
Waveform 4
MHz
Waveform 1, 2
4.4
5.9
5.5
6.2
5.9
5.5
6.1
5.2
6.0
4.8
5.3
4.8
4.8
6.6
5.9
7.0
6.5
6.0
6.5
6.0
6.5
5.8
6.0
5.4
5.4
7.5
3.5
ns
Waveform 1, 2
4.6
ns
Waveform 1, 2
4.1
ns
Waveform 1, 2
3.8
ns
Waveform 5, 6
3.5
ns
Waveform 5, 6
3.4
ns
Test Circuit and
Waveforms
ns
t
SK
(o)
Waveform 3
0.5
1.0
1.5
ns
t
SK
(p)
Waveform 2
0.5
1.0
1.0
ns
NOTES:
1.
t
PN
actual – t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or HL.
Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
2. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
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