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參數(shù)資料
| 型號(hào)： | FASTCARD2 |
| 英文描述： | FASTcard 2 - FDDI PC/AT-Based SUPERNET 2 Technology Card (FASTcard). Dual Attachment Concentrator Board Set and Software Package |
| 中文描述： | FASTcard 2 -光纖分布式數(shù)據(jù)介面的PC / AT - 2技術(shù)基于超網(wǎng)卡（FASTcard）。雙連接集中局設(shè)置和軟件包 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 27K |
| 代理商： | FASTCARD2 |
AMD
P R E L I M I N A R Y
5-4
The SUPERNET 2 Family for FDDI 1994 Data Book
MP Card
DAS Card
16047B-1
Optical
Data Link
Optical
Data Link
32Kx8 SRAM
32Kx8 SRAM
32Kx8 SRAM
32Kx8 SRAM
32Kx8 SRAM
P
XTAL
Am79C830A
FORMAC
Plus
Am79C864
PLC
Am79C864
PLC
Advanced Micro Devices
FASTcard 2 DAS
Primary-In
Secondary-Out
Secondary-In
Primary-Out
External Interface
PDR
PDT
PDR
PDT
Optical
Data Link
Optical
Data Link
Advanced Micro Devices
FASTcard 2 Master Port
External
Interface
O
D
O
D
O
D
O
D
P
P
P
P
PDR
PDT
PDR
PDT
Optical
Data Link
Optical
Data Link
Optical
Data Link
Optical
Data Link
Am79C864
PLC
Am79C864
PLC
Am79C864
PLC
Am79C864
PLC
HARDWARE
The FASTcard 2 hardware consists of two main sec-
tions; the FDDI station logic and the associated inter-
face logic. The FDDI station logic consists of the
SUPERNET 2 chip set, the buffer memory, and the fiber
optic transmitter/receiver. The chip set performs the
buffer memory management tasks in addition to the
MAC and PHY layer functions. The buffer memory on
the FASTcard 2 hardware consists of 128K bytes organ-
ized as 32K x 36 bits. Buffer memory control logic pro-
vides the host CPU with direct access to the FDDI buffer
memory via the host DMA interface of the FORMAC
Plus (Am79C830A).
The interface logic consists of the AT bus interface, the
host-buffer memory interface, counter and interrupt
logic, Connection Management (CMT) logic, and FDDI
configuration hooks and control logic. The CMT logic is
responsible for gathering connection statistics of the
network to report them to the station. The DAS board
provides interface signals to additional MP cards when
constructing a concentrator. The DAS board makes use
of the AT’s processor as the host and node controller.
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