參數(shù)資料
型號(hào): FAN8623
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 運(yùn)動(dòng)控制電子
英文描述: 12V Spindle Motor and Voice Coil Motor Driver(12V電源的主軸電機(jī)和語音線圈電機(jī)驅(qū)動(dòng)器)
中文描述: VOICE COIL MOTOR CONTROLLER, 1.2 A, PQFP52
封裝: 14 X 14 MM, HEAT SINK, QFP-48
文件頁數(shù): 16/35頁
文件大?。?/td> 443K
代理商: FAN8623
FAN8623; PRELIMINARY
16
Application Information
Spindle Motor Drive Circuit
The FAN8623 is a combination chip consisting of spindle motor and voice coil motor designed for HDD system. According to
the spindle conditions, the digital ASIC provides optimum control signals (Start-up, commutation, speed control, and commu-
tation mode) to the FAN8623.
Back-EMF (BEMF) signal of the spindle motor is fed back to ASIC via FG line. The MCLK and PWM signals are used to
determine the commutation timing and to control the spindle speed, respectively.
Spindle Driver
The spindle includes both low and high side drivers (H-bridge) for a three-phase sensorless brushless DC motor. To reduce the
saturation voltage, the vertical PNP transistor is used as the high side driver.
Frequency Generation (FG)
FG stands for Frequency Generation. It is the output signal to the ASIC.
It contains important information about the motor speed.
According to the FG frequency, the digital ASIC provides different motor clock signals to the motor drive IC via MCLK.
It checks the motor speed to send the VCM enable signal via CNTL3.
FG frequency (Hz), motor speed (rpm) and pole number are directly related as shown below in the three phase motor.
FG frequency(Hz) = motor speed(rpm)
×
pole number / 2
×
3 / 60
In a typical application,(8 pole motor)
FG frequency = 5400
×
8 /2
×
3 / 60 = 1080 Hz
MCLK & Mask
The MCLK is a motor clock used as the standard clock signal for the proper commutation timing of the spindle motor. It is
supplied by the ASIC.
As shown in table 1, it has different delay times depending on the mode of the spindle.
Table 1.
After the FG_Edge signal detection, the MCLK occurs after a half FG_Edge delay time in the acceleration mode and 1/ 32
FG_Edge delay time in the soft commutation mode.
MCLK (Td)
2ms (External ASIC)
FG(n-1) / 2
FG(n-1) / 32
MASK
1ms
FG(n-1) / 4
344.45
m
s
Commutation
Hard
Hard
Soft
Start-up mode
Acceleration mode
Running mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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