參數(shù)資料
型號： FAN53168MTC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 穩(wěn)壓器
英文描述： 6-Bit VID Controlled 2-4 Phase DC-DC Controller
中文描述： SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28
封裝： TSSOP-28
文件頁數(shù)： 16/28頁
文件大小： 397K
代理商： FAN53168MTC
FAN53168
PRODUCT SPECIFICATION
16
REV. 1.0.0 6/9/03
Figure 4. VID On-the-Fly Waveforms, Circuit of Figure 1,
VID Change = 5mV, 5μs, 50 steps,
I
OUT
Change = 5A to 65A
Power Good Monitoring
The Power Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indi-
cates that the output voltage is within the nominal limits
speci
fi
ed in the speci
fi
cations above based on the VID volt-
age setting. PWRGD will go low if the output voltage is out-
side of this speci
fi
ed range. PWRGD is blanked during a
VID OTF event for a period of 250μs to prevent false signals
during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components
of the supply, the PWM outputs will be driven low (turning
on the low-side MOSFETs) when the output voltage exceeds
the upper Power Good threshold. This crowbar action will
stop once the output voltage has fallen below the release
threshold of approximately 450mV.
Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high side MOSFET, this
action will current limit the input supply or blow its fuse,
protecting the microprocessor from destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher than its
logic threshold for the FAN53168 to begin switching. If
UVLO is less than the threshold or the EN pin is a logic low,
the FAN53168 is disabled. This holds the PWM outputs at
ground, shorts the DELAY capacitor to ground, and holds
the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be con-
nected to the OD# pins of the FAN53418 drivers. Because
ILIMIT is grounded, this disables the drivers such that both
DRVH and DRVL are grounded. This feature is important to
prevent discharging of the output capacitors when the
controller is shut off. If the driver outputs were not disabled,
then a negative voltage could be generated on the output due
to the high current discharge of the output capacitors through
the inductors.
APPLICATION INFORMATION
The design parameters for a typical Intel VRD10-compliant
CPU application are as follows:
Input voltage (V
IN
) = 12 V
VID setting voltage (V
VID
) = 1.500 V
Duty cycle (D) = 0.125
Nominal output voltage at no load (V
ONL
) = 1.480 V
Nominal output voltage at 65 A load (V
OFL
) = 1.3955 V
Static output voltage drop based on a 1.3 m
load line
(R
O
) from no load to full load
(V
D
) = V
ONL
–
V
OFL
= 1.480 V
–
1.3955 V = 84.5 mV
Maximum Output Current (I
O
) = 65 A
Maximum Output Current Step (
I
O
) = 60A
Number of Phases (n) = 3
Switching frequency per phase (f
SW
) = 228 kHz
Setting the Clock Frequency
The FAN53168 uses a fixed-frequency control architecture.
The frequency is set by an external timing resistor (R
T
).
The clock frequency and the number of phases determine the
switching frequency per phase, which relates directly to
switching losses and the sizes of the inductors and input
and output capacitors. With n = 3 for three phases, a clock
frequency of 684kHz sets the switching frequency of each
phase, f
SW
, to 228kHz, which represents a practical trade-off
between the switching losses and the sizes of the output filter
components. TPC 1 shows that to achieve a 684kHz oscilla-
tor frequency, the correct value for R
T
is 301k
. Alterna-
tively, the value for R
T
can be calculated using:
where 5.83pF and 1.5M
are internal IC component
values. For good initial accuracy and frequency stability,
it is recommended to use a 1% resistor.
Soft-Start and Current Limit Latch-Off Delay Times
Because the soft-start and current limit latch off delay
functions share the DELAY pin, these two parameters must
be considered together. The first step is to set C
DLY
for the
soft-start ramp. This ramp is generated with a 20μA internal
current source. The value of R
DLY
will have a second order
impact on the soft-start time because it sinks part of the
current source to ground. However, as long as R
DLY
is kept
greater than 200k
, this effect is minor. The value for C
DLY
can be approximated using:
R
T
n
f
SW
×
5.83pF
×
(
)
------------------
–
--------------------------------------------------------------------------
=
(1)
C
DLY
20
μ
A
V
DLY
-----------------------
–
t
V
VID
------------
×
=
(2)
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FAN53168MTCX 功能描述:DC/DC 開關(guān)控制器 Buck Controller 2to4 Phs VID Sync RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
FAN53180 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:6-Bit VID Controlled 2-4 Phase DC-DC Controller
FAN53180MTC 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:6-Bit VID Controlled 2-4 Phase DC-DC Controller
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