參數(shù)資料
型號: FAN53168
廠商: Fairchild Semiconductor Corporation
英文描述: 6-Bit VID Controlled 2-4 Phase DC-DC Controller
中文描述: 6位VID控制2-4相DC - DC控制器
文件頁數(shù): 20/28頁
文件大?。?/td> 397K
代理商: FAN53168
FAN53168
PRODUCT SPECIFICATION
20
REV. 1.0.0 6/9/03
capacitors must be increased. One should note for this multi-
mode control technique,
all-ceramic” designs can be used
as long as the conditions of Equations 11, 12 and 13 are
satisfied
.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are V
GS(TH)
, Q
G
, C
ISS
, C
RSS
and R
DS(ON)
.
The minimum gate drive voltage (the supply voltage to the
FAN53418) dictates whether standard threshold or logic-
level threshold MOSFETs must be used. With V
GATE
~10V,
logic-level threshold MOSFETs (V
GS(TH)
< 2.5V) are
recommended. The maximum output current I
O
determines
the R
DS(ON)
requirement for the low-side (synchronous)
MOSFETs. With the FAN53168, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (n
SF
). With conduction losses being dominant,
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
R
) and average total output current
(I
O
):
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can
fi
nd
the required R
DS(ON)
for the MOSFET. For D-PAK
MOSFETs up to an ambient temperature of 50
°
C, a safe
limit for P
SF
is 1W-1.5W at 125
°
C junction temperature.
Thus, for our example (65A maximum), we
fi
nd R
DS(SF)
(per MOSFET) < 8.7m
. This R
DS(SF)
is also at a junction
temperature of about 125
°
C, so we need to make sure we
account for this when making this selection. For our
example, we selected two lower side MOSFETs at 8.6m
each at room temperature, which gives 8.4m
at high
temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio of
the feedback to input needs to be small (less than 10% is
recommended) to prevent accidental turn-on of the synchro-
nous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN53418). The
output impedance of the driver is about 2
and the typical
MOSFET input gate resistances are about 1
– 2
, so a total
gate capacitance of less than 6000pF should be adhered to.
Since there are two MOSFETs in parallel, we should limit
the input capacitance for each synchronous MOSFET to
3000pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switch-
ing losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and off, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where n
MF
is the total number of
main MOSFETs:
Here, R
G
is the total gate resistance (2
for the FAN53418
and about 1
for typical high speed switching MOSFETs,
making R
G
= 3
) and C
ISS
is the input capacitance of the
main MOSFET. It is interesting to note that adding more
main MOSFETs (n
MF
) does not really help the switching
loss per MOSFET since the additional gate capacitance
slows down switching. The best way to reduce switching
loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where R
DS(MF)
is the ON-resistance of the
MOSFET:
Typically, for main MOSFETs, one wants the highest speed
(low C
ISS
) device, but these usually have higher ON-resis-
tance. One must select a device that meets the total power
dissipation (about 1.5 W for a single D-PAK) when combin-
ing the switching and conduction losses.
For our example, we have selected a Fairchild FD6696 as the
main MOSFET (three total; n
MF
= 3), with a C
iss
= 2058 pF
(max) and R
DS(MF)
= 15m
(max at T
J
= 125°C) and a
Fairchild FDD6682 as the synchronous MOSFET (six total;
n
SF
= 6), with C
iss
= 2880pF (max) and R
DS(SF)
= 11.9m
(max at T
J
= 125°C). The synchronous MOSFET C
iss
is less
than 3000 pF, satisfying that requirement. Solving for the
power dissipation per MOSFET at I
O
= 65 A and I
R
= 8.86A
yields 1.24W for each synchronous MOSFET and 1.62W for
each main MOSFET. These numbers work well considering
there is usually more PCB area available for each main
MOSFET versus each synchronous MOSFET.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
G
for
the MOSFETs and is given by the following, where Q
GMF
is
the total gate charge for each main MOSFET and Q
GSF
is the
total gate charge for each synchronous MOSFET:
P
SF
1
D
(
)
I
SF
---------
2
------
n
--------------
I
R
×
SF
2
×
+
×
R
DS SF
)
×
=
(15)
P
S MF
)
2
f
SW
×
V
----------------------
I
O
×
MF
×
R
G
×
n
----------
C
ISS
×
×
=
(16)
P
C MF
)
D
I
MF
----------
2
------
n
--------------
I
R
×
MF
2
×
+
×
R
DS MF
)
×
=
(17)
P
DRV
f
n
------------
n
MF
Q
GMF
n
SF
Q
GSF
×
+
×
(
)
I
CC
+
×
V
CC
×
=
(18)
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