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參數(shù)資料
| 型號： | FAN5018B |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 6-Bit VID Controller 2-4 Phase VR10.X Controller |
| 中文描述： | 6期西元控制器2-4位的VR10.X控制器 |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 509K |
| 代理商： | FAN5018B |
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PRODUCT SPECIFICATION
FAN501
8
B
REV. 1.0.0 Jul/15/05
5
Electrical Specifications
(V
CC
= 12V, T
A
= 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Parameter
Error Amplifier
Symbol
Conditions
Min.
Typ.
Max.
Units
Output Voltage Range
V
COMP
V
FB
0.5
3.5
V
Accuracy
Relative to DAC Setting,
referenced to FBRTN,
CSSUM = CSCOMP,
Test Circuit 3
VRM10
VRM9
-14
-17
+14
+17
mV
Line Regulation
Δ
V
FB
I
FB
I
FBRTN
I
O(ERR)
GBW
VCC=10V to 14V
0.05
%
Input Bias Current
-17
-15
-13
μA
FBRTN Current
150
180
μA
Output Current
FB forced to V
OUT
– 3%
COMP = FB ( See Note 2)
300
500
μA
Gain Bandwidth Product
20
MHz
DC Gain
VID Inputs
C
COMP
= 10pF ( See Note 2)
77
dB
Input Low Voltage
V
IL(VID)
VRM10
VRM9
0.4
0.8
V
V
Input High Voltage
V
IH(VID)
VRM10
VRM9
0.8
2.0
V
V
Input Current, VID Low
I
IL(VID)
I
IH(VID)
R
VID
VID(X) = 0V
-30
-20
μA
Input Current, VID High
VID(X) = 1.15V
-2
2
μA
k
Ω
Pull-up Resistance
Internal
35
60
115
Internal Pull-up Voltage
VRM10
VRM9
1.0
2.2
1.15
2.4
1.26
2.6
V
V
VID Transition Delay
Time
2
VID Code Change to FB Change
400
ns
“No CPU” Detection
Turn-off Delay Time
2
VID Code Change to 11111X to PWM
going low
400
ns
VID Table Select
Vtblsel
To select VRM9 table
To select VRM10 table (becomes VID5)
4
3.5
V
V
Oscillator
Frequency
f
OSC
f
PHASE
200
4000
kHz
Frequency Variation
T
A
= +25°C, R
T
= 250k
Ω
, 4-Phase
T
A
= +25°C, R
T
= 115k
Ω
, 4-Phase
T
A
= +25°C, R
T
= 75k
Ω
, 4-Phase
R
T
= 100k
Ω
to GND
V
RAMPADJ
= Vdac = +2K (Vin–Vdac)/
(Rr+2k) @ 20μA
155
200
400
600
245
kHz
kHz
kHz
Output Voltage
V
RT
V
RAMPADJ
1.9
2.0
2.1
V
RAMPADJ Pin Accuracy
-50
+50
mV
RAMPADJ Input Current
Current Sense Amplifier
I
RAMPADJ
Current into RAMPADJ pin
0
100
μA
Offset Voltage
V
OS(CSA)
I
BIAS(CSA)
GBW
CSSUM–CSREF, Test Circuit 1
-3.0
+3.0
mV
Input Bias Current
-50
+50
nA
Gain Bandwidth Product
COMP = FB ( See Note 2)
10
MHz
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
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