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參數(shù)資料
| 型號(hào)： | FAN4931IP5X |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大小： | 0K |
| 描述： | IC AMP VFA RRIO CMOS SC70-5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 3 V/µs |
| 增益帶寬積： | 3.7MHz |
| -3db帶寬： | 3.7MHz |
| 電流 - 輸入偏壓： | 5pA |
| 電流 - 電源： | 200µA |
| 電流 - 輸出 / 通道： | 33mA |
| 電壓 - 電源，單路/雙路(±)： | 2.3 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP（5 引線），SC-88A，SOT-353 |
| 供應(yīng)商設(shè)備封裝： | SC-70-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FAN4931IP5XFSDKR |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN4931 Rev. 1.0.2
9
FAN4931
—
Ultra-Lo
w
Cost,
Ra
il-
to-Rail
I/O,
CM
OS
Amplifier
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance. Fairchild evaluation boards
help guide high-frequency layout and aid in device testing
and characterization. Follow the steps below as a basis
for high-frequency layout:
Include 6.8 μF and 0.01 μF ceramic capacitors.
Place the 6.8 μF capacitor within 0.75 inches of the
power pin.
Place the 0.01 μF capacitor within 0.1 inches of the
power pin.
Remove the ground plane under and around the part,
especially near the input and output pins, to reduce
parasitic capacitance.
Minimize all trace lengths to reduce series inductances.
Refer to the evaluation board layouts shown in Figure 24-
Figure 26 for more information.
When evaluating only one channel, complete the
following on the unused channel:
Ground the non-inverting input.
Short the output to the inverting input.
Evaluation Board Information
The following evaluation board is available to aid in the
testing and layout of this device.
Evaluation
Board
Description
Products
FAN4931-011
Single-Channel,
Dual-Supply,
5 -Lead SC70
FAN4931IP5X
Evaluation board schematics are shown in Figure 24;
layouts are shown in Figure 25-Figure 26.
Figure 24. Evaluation Board Schematic
Board Layout Information
Figure 25. Top Side
Figure 26. Bottom Side
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