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參數(shù)資料
| 型號(hào)： | FAN4852IMU8X |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP R-R 9MHZ DUAL LP 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 6.2 V/µs |
| 增益帶寬積： | 9MHz |
| 電流 - 輸入偏壓： | 0.1pA |
| 電壓 - 輸入偏移： | 300µV |
| 電流 - 電源： | 900µA |
| 電流 - 輸出 / 通道： | 90mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN4852 Rev. 4.0.0
14
FAN48
52
—
9MHz
Low-Power
Dual
CMOS
Amplifier
Layout Considerations
General layout and supply bypassing play major roles
in high-frequency performance. Fairchild evaluation
boards help guide high-frequency layout and aid in
device testing and characterization. Follow the steps
below as a basis for high-frequency layout:
1.
Include 6.8μF and 0.01μF ceramic capacitors.
2.
Place the 6.8μF capacitor within 0.75 inches of
the power pin.
3.
Place the 0.01μF capacitor within 0.1 inches of
the power pin.
4.
Remove the ground plane under and around the
part, especially near the input and output pins, to
reduce parasitic capacitance.
Minimize
all
trace
lengths
to
reduce
series
inductances.
Refer to the evaluation board layouts shown in Figure
33 for more information.
When evaluating only one channel, complete the
following on the unused channel:
1.
Ground the non-inverting input.
2.
Short the output to the inverting input.
Evaluation Board
Description
FAN4852-010
Single Channel, Dual Supply
Figure 33. Evaluation Board Schematic
-
+
3
2
1
8
4
OUT 1
SMA
+IN 1
SMA
V-
-
+
5
6
7
8
4
V+
V-
C9
1uF
- IN 1
SMA
R-C8
10K
V-
R6 0.0
R-C4
10K
R7 10K
R11
50
R3
10K
C12
0.1uF
OUT 2
SMA
- IN 2
SMA
V+
R5
50
R2 0.0
V+
R1 10K
C10
0.1uF
PWRCON
V+
GND
V-
C11
1uF
R8 0.0
R9
10K
R10 0.0
R4 0.0
+IN 2
SMA
R12 0.0
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