FA7622CP(E)
6
4. Timer and latch circuit for overload protection
Figure 9 shows the timer and latch circuit for overload
protection and Fig. 10 shows its timing during an overload.
If the power supply output decreases due to an overload, the
error amplifier output decreases. If the voltage decreases to
less than 0.3V, the switch that clamps the CP pin voltage to
the ground disconnects. This charges capacitor Cp from the
REF pin through the resistor Rcp and the CP pin voltage
increases. When the voltage reaches 1.25V, OUT1 (OUT2)
voltage is clamped to ground.
The N-channel MOSFET (or NPN transistor) connected to the
OUT1 (or OUT2) is turned OFF and cuts off the power supply.
The time t
L
from when the circuit is overloaded until the power
supply is cut off can be determined as follows:
(9)
.................
t
L
(m
S
) = 0.67C
P
(
μ
F) R
CP
(k
)
5. Overcurrent limiting circuit
This is a pulse-by-pulse overcurrent limiting circuit which
detects and limits the peak of each drain current pulse from the
main switching transistor (MOSFET).
Figure 11 shows the overcurrent limiting circuit and Fig. 12
shows its timing.
This circuit detects a drain current with a voltage sampling
resistor Rs. If a voltage lower than the V
CC1
pin voltage by
210mV or more is input to OCL1 (OCL2), the OUT1 (OUT2) is
clamped to ground. At the same time, DT1 (DT2) is raised to
the reference voltage V
REF
. (This reduces the duty-cycle to
0%)
This circuit has hysteresis to prevent noise from causing
malfunction.
The R
S
voltage which is propotional to drain current is limited
to 210mV (typ.) and released at 170mV (typ).
Fig. 9
Fig. 10
Fig. 11
Fig. 12
2
OUT1
(OUT2)
OCL1
(OCL2)
VCC1
-0.21V
REF
DT1
(DT2)
VCC1
D
I
1
Rs
OUT1
(OUT2)
Time
VCC1
VCC1
-0.2V
OCL1
(OCL2)
(Similar to I
D
)
Voltage waveforms
PWM output
FB1(FB2)
DT1(DT2)
Time
CP
CT
1.25V
(Threshold voltage
of CP pin)
Voltage waveforms
20
1
2
1
2
1.25V
C
P
S1
REF
OUT1
(OUT2)
R
CP
FB1
(FB2)
0.3V
CP