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參數(shù)資料
| 型號(hào)： | FA3686 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | For Switching Power Supply Control |
| 中文描述： | 對(duì)于開關(guān)電源控制 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 389K |
| 代理商： | FA3686 |
FA3686V
15
10. PGS circuit
The PGS pin is an open drain output of Nch MOSFET for
transmitting fault signals of the power supply. The PGS circuit is
enabled when Vcc voltage is over the operating threshold
voltage (approximately 1V). The Nch MOSFET turns ON and
the PGS pin is connected to GND if any of the following three
conditions occurs:
1) the V
CC
voltage is below the threshold voltage (V
CC
increasing: 2.35V typ.; V
CC
decreasing: 2.25V typ.), 2) UVLO
turns on (V
CC
=2.1V or below), 3) IC is off latch mode.
The operation sequence is shown in Fig. 8.
As shown in Fig. 8, in the case of increasing the Vcc voltage
with the voltage V applied to the PGS pin, when the Vcc voltage
reaches 1V, PGS circuit is enabled and detects that the Vcc
voltage is not enough high. Then PGS circuit turns the Nch
MOSFET on and output fault signal. The fault signal is
cancelled when the V
CC
voltage exceeds 2.35V (typ.).
In the case that the V
CC
voltage exceeds 2.53V (typ.) and the
IC is off latch mode, the PSG circuit detects it as abnormal and
the Nch MOSFET is turned on.
In the case of decreasing the V
CC
voltage, the circuit sends out
fault signals when the V
CC
voltage is below 2.25V (typ.) and
continues to output until the V
CC
voltage reaches below the
PGS circuit operation threshold voltage of approximately 1V.
(Under the V
CC
voltage of 1V, the circuit does not operate
normally.)
Fig. 8
+
5
PGS
11
V
UVLO
VPGS
Timer latch
V
CC
decreasing
V
CC
increasing
1V
V
PGS
voltage 2.25V
Hysteresis voltage
P
p
Vcc voltage stable state
Off latch mode
Off latch mode reset
PGS operation
PGS operation
PGS operation
Vcc
V
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