
Vicor Corporation Tel: 800-735-6200   vicorpower.com
VI Chip Evaluation Board  
Rev. 1.1
Page 3 - 4
Specifications cont.
R1
–IN
TP1 
F1
C5
C6 –7
C10 –17
R3
R4
R5
R6
TP2
TP3
TP5
J2
–OUT
+OUT
+IN
TP4
J1
C1– 4
B1
0.4 
μ
H
B2
Vin 
Vout
Vf
–Out
+In
–In
VC
PC
TM
IL
NC
VH
SC
PR
SG
OS
NC
CD
PRM-AL
-In
PC
VC
TM
+In
-Out
+Out
VTM
+Out
-Out
K
Ro
Figure 4 
— EVAL Board Schematic Diagram
The functionality of the FPAEval Board has now been 
verified 
over the entire line and load operating range.
As you can see, the PRM’s Adaptive Loop regulates the output
of the VTM without sense lines. You may monitor the Vf View
(J1) while increasing the load current: the Vf voltage increases
with the load current, compensating for the insertion loss due
to the VTM output resistance.
Connecting the PRM’s PC (TP1) to the -IN disables the output
of the Evaluation Board. Use CAUTION when probing,
especially on or near TP1 and VC on the PRM. Accidental
shorting between these two points can cause permanent
damage.
The Evaluation Board has provisions for changing the factory
set output voltage, the current limit, the Adaptive Loop Gain,
and the turn on ramp rate. Refer to the PRM data sheet for
more information on these features. Refer to Figure 4 for a
Schematic representation of the FPAEvaluation Board.
Locations for these components are shown in Figure 3.
For assistance, feel free to contact Vicor Applications
Engineering at 800-927-9474
This Evaluation Board is being provided as a means to facilitate
successful demonstration of Factorized Power Architecture and its
elements. Vicor assumes no obligation or liability for the advice given,
or results obtained. All such advice being given and accepted is at
user’s risk.
Figure 3 
— FPA EVAL Board configuration may vary
Location for 0603 soft
start capacitor, SC
Location for 0603 output
voltage set resistor, OS
Location for 0603
compensation device resistors, CD
Position for 0603
current limit
adjust resistor, IL
PRELIMINARY