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參數(shù)資料
| 型號(hào)： | F29C51001T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1MEGABIT(131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY |
| 中文描述： | 1MEGABIT（131072 × 8位）5伏的CMOS閃存 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | F29C51001T |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
SyncMOS
F
29C51001T/
F
29C51001B
3
F
29C51001T/
F
29C51001B
V1.0
May 1999
Functional Block Diagram
Capacitance
(1,2)
NOTE:
1.
2.
Capacitance is sampled and not 100% tested.
T
A
= 25
°
C, V
CC
= 5V
±
10%, f = 1 MHz.
Latch Up Characteristics
(1)
NOTE:
1.
Includes all pins except V
CC
CC
= 5V, one pin at a time.
AC Test Load
Symbol
Parameter
Test mSetup
Typ.
Max.
Units
C
IN
Input Capacitance
V
IN
= 0
6
8
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
8
10
pF
Parameter
Min.
Max.
Unit
Input Voltage with Respect to GND on A
9
, OE
-1
+13
V
Input Voltage with Respect to GND on I/O, address or control pins
-1
V
CC
+ 1
V
V
CC
Current
-100
+100
mA
Address buffer & latches
A
0
–A
16
51001-05
I/O Buffer & Data Latches
I/O
0
–I/O
7
Y-Decoder
1,048,576 Bit
Memory Cell Array
X-Decoder
Control Logic
CE
OE
WE
51001-06
IN3064 or Equivalent
IN3064
or Equivalent
2.7 k
6.2 k
+5.0 V
IN3064 or Equivalent
IN3064 or Equivalent
C
L
= 100 pF
Device Under
Test
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