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绯诲垪锛� EX
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eX Family FPGAs
Revision 10
1-23
Output Buffer Delays
AC Test Loads
Table 1-13 Output Buffer Delays
Figure 1-15 AC Test Loads
D
To AC Test Loads (shown below)
PAD
E
TRIBUFF
GND
50%
Out
1.5 V
50%
1.5 V
En
GND
50%
Out
1.5 V
50%
10%
En
GND
50%
Out
GND
1.5 V
50%
90%
VOL
VCC
VOH
t
DLH
t
DHL
VOL
VCC
t
ENZL
t
ENLZ
VCC
VOH
t
ENZH
t
ENHZ
In
R to VCC for tPZL
R to GND for t
PHZ
R = 1 k
R to VCC for t
PLZ
R to GND for t
PHZ
R = 1 k
GND
35 pF
GND
35 pF
5 pF
To the output
under test
To the output
under test
To the output
under test
Load 1
(used to measure
propagation delay)
Load 2
(Used to measure enable delays)
Load 3
(Used to measure disable delays)
VCC
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