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參數(shù)資料
| 型號： | EVM-1702 |
| 英文描述： | EVM-1702 - EVALUATION MODULE |
| 中文描述： | 的EVM - 1702 -評估模塊 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 329K |
| 代理商： | EVM-1702 |
7
EVM-1702
THEORY OF OPERATION
The super HiFi DAC board EVM-1702 requires only a
power supply and a digital audio input signal. The system
outputs a stereo audio signal with excellent sound and
performance.
DIGITAL SECTION
The digital section contains a Digital Audio Interface re-
ceiver IC (CS8412) and digital filter/HDCD decoder PMD-
100. See Figure 1.
The CS8412 generates a 256fS system clock and recovers
PCM audio data to provide the PMD-100 with a digital
audio input signal. The PMD-100 has two major functions:
as an oversampling digital filter and an HDCD decoder
which outputs 8X, 20-bit oversampling data to the DAC
section.
An external timing circuit containing an HC04 and HC595
detects de-emphasis control and sampling frequency(fS) in-
formation.
DIGITAL ISOLATOR SECTION
ISO150 is a two-channel isolated data coupler capable of a
data rate of 80MB with a 1500V rated isolation voltage.
Any digital noise in the digital section can be completely
isolated from the DAC/analog section by the ISO150. The
analog section can be operated with a low noise power
supply and ground.
DAC SECTION
The PCM1702 has both digital and analog power supply pins.
To reject switching noise at the DAC, EVM-1702 uses a
ripple filter circuit for power supply filtering. See Figure 5.
Superior performance and sound quality are produced by
combining the parallel connection of 4 DACs per channel.
This parallel connection technique produces very low THD+N
performance (up to –100dB) and wide dynamic range (up
to 112dB). The user may configure the system with up to
4 PCM1702s per channel. The parallel connection of ‘N’
PCM1702s (where ‘N’ = 1, 2, 3, 4) can be determined by
the user. Feedback resistors RF1 and RF2 in the I/V section
should be changed according to the number (‘N’) of
PCM1702 DACs. The output voltage (Vp-p) is given by the
following equation:
Vp-p =
±1.2mA x N x RF
1, 2
I/V SECTION
The high speed Difet OPA627 is the best op amp for the
I/V amp section due to its high speed settling, slew rate,
low THD+N, and low noise performance. The feedback
resistor (RF) provides an output voltage as described in the
DAC section. The feedback capacitor (CF) determines the
closed-loop cut-off frequency.
SECOND-ORDER POST LPF SECTION
After I/V conversion, the output signal still contains out-of-
band noise. In order to reject this out-of-band noise, EVM-
1702 uses a 2nd-order inverting, active low pass filter with
an OPA2604 (see Figure 4). The OPA2604 has superior
sound quality with very low THD+N performance. This dual
op amp is designed for high performance audio applications.
The cut-off frequency of this LPF is designed to 80kHz
where the digital filter has more than 100dB stopband
attenuation.
Optional 2nd PLL
The dynamic performance of the D/A conversion system is
influenced by clock jitter and the sensitivity of this jitter is
mainly given by the architecture of the D/A converter. The
EVM-1702 uses a low jitter digital audio interface receiver
(CS8412), in conjunction with a multi-bit DAC (PCM1702),
to achieve superior performance without the use of a re-
clocking circuit.
The EVM-1702 has an optional 2nd PLL circuit (not in-
stalled) which can be populated if the user so chooses. Refer
to Figure 1. The clock selection can be controlled by JP1
through JP3, normally set to side 1.
OPTIONAL SINGLE-ORDER POST LPF
Instead of a 2nd-order low pass filter, a simple 1st-order, RC
passive low pass filter may be constructed. The filter is
composed of RP1, 2 and CP1, 2, which can be calculated by
the following formula:
fC =
NOTE: When using a single-order RC circuit on the EVM-
1702, the OPA2604 must be removed and resistors RP5, 6,
should be replaced with 0
resistors (short circuits). Sound
quality differences between the 1st-order RC filter response
versus a 2nd-order active filter response are objective and
should be decided by the user.
HDCD Decoder
The HDCD decoded output signal level is 6dB lower than
the normal CD output due to HDCD encoding/decoding
architecture.
Normal CD: 2Vrms typ
HDCD CD: 1Vrms typ
In general, this 6dB loss can be compensated by any gain
control circuit. In the case of the EVM-1702, it does not
include a compensation circuit for the 6dB loss due to noise
or distortion considerations of the overall system.
1
(2
π) (RP
1, 2
) (CP
1, 2
)
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