參數(shù)資料
型號(hào)： EVAL-SSM2518Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/48頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR SSM2518
標(biāo)準(zhǔn)包裝： 1
系列： *
SSM2518
Data Sheet
Rev. A | Page 36 of 48
DRC CONTROL 1 REGISTER
Address: 0x0A, Reset: 0x7C, Name: DRC_Control_1
Table 23. Bit Descriptions for DRC_Control_1
Bits
Bit Name
Settings
Description
Reset
Access
7
RESERVED
Reserved.
0x0
RW
6
PRE_VOL
DRC Placement. This determines the placement of the DRC block in the
signal chain. When placed before the volume control, the thresholds are
relative to the input signal. When placed after the volume control, the
thresholds are relative to the output signal level. All thresholds are 6 dB
higher when placed after the volume control.
0x1
RW
0
DRC operates after the volume control
1
DRC operates before the volume control
5
LIM_EN
Limiter Enable. With the limiter enabled, the DRC_LT threshold (Bits[7:4] in
Register 0x0C) must be set.
0x1
RW
0
Limiter disabled
1
Limiter enabled
4
COMP_EN
Compressor Enable. With the compressor enabled, the DRC_CT and
DRC_SMAX thresholds (Bits[3:0] in Register 0x0C and Bits[7:4] in
Register 0x0E) must be set.
0x1
RW
0
Compressor disabled
1
Compressor enabled
3
EXP_EN
Expander Enable. With the expander enabled, the DRC_ET and DRC_SMIN
threshold values (Bits[7:4] in Register 0x0D and Bits[3:0] in Register 0x0E)
must be set.
0x1
RW
0
Expander disabled
1
Expander enabled
2
NG_EN
Noise Gate Enable. With the noise gate enabled, the DRC_NT threshold
value (Bits[3:0] in Register 0x0D) must be set.
0x1
RW
0
Noise gate disabled
1
Noise gate enabled
[1:0]
DRC_EN
Master DRC Enable. This must be enabled for any of the DRC features to
function.
0x0
RW
00
DRC disabled
01
Left channel DRC enabled
10
Right channel DRC enabled
11
Left and right channel DRC enabled
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