參數(shù)資料
型號: EVAL-CN0204-SDPZ
廠商: Analog Devices Inc
文件頁數(shù): 29/32頁
文件大?。?/td> 0K
描述: BOARD CFTL AD5662 AD5751
設計資源: CN-0204 CFTL Eval/Design Support
標準包裝: 1
系列: Circuits from the Lab™
主要目的: 參考設計,模擬輸出模塊
嵌入式:
已用 IC / 零件: AD5662,AD5751,ADuM1301,ADuM5401
主要屬性: 隔離
已供物品:
AD5751
Data Sheet
Rev. B | Page 6 of 32
Parameter 1
Min
Typ
Max
Unit
Test Conditions/Comments
Gain TC4
±1
ppm FSR/°C
Full-Scale Error
0.1
+0.1
% FSR
0.07
±0.02
+0.07
% FSR
TA = 25°C
Full-Scale TC4
±2
ppm FSR/°C
OUTPUT CHARACTERISTICS4
Current Loop Compliance Voltage
0
AVDD 2.75
V
Resistive Load
Chosen such that compliance is not
exceeded
Inductive Load
See test conditions/comments column
H
Needs appropriate capacitor at higher
inductance values; see Driving Inductive
Loads section
Settling Time
4 mA to 20 mA, Full-Scale Step
8.5
s
250 load
120 A Step, 4 mA to 20 mA Range
1.2
s
250 load
DC PSRR
1
A/V
Output Impedance
130
M
DIGITAL INPUTS4
JEDEC compliant
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Input Current
1
+1
A
Per pin
Pin Capacitance
5
pF
Per pin
DIGITAL OUTPUTS4
FAULT, IFAULT, TEMP, VFAULT
VOL, Output Low Voltage
0.4
V
10 k pull-up resistor to DVCC
0.6
V
At 2.5 mA
VOH, Output High Voltage
3.6
V
10 k pull-up resistor to DVCC
SDO
VOL, Output Low Voltage
0.5
V
Sinking 200 A
VOH, Output High Voltage
DVCC 0.5
V
Sourcing 200 A
High Impedance Output
Capacitance
3
pF
High Impedance Leakage Current
1
+1
A
POWER REQUIREMENTS
AVDD
10.8
55
V
DVCC
Input Voltage
2.7
5.5
V
AIDD
4.4
5.6
mA
Output unloaded, output disabled
5.2
6.2
mA
Current output enabled
5.2
6.2
mA
Voltage output enabled
DICC
0.3
1
mA
VIH = DVCC, VIL = GND
Power Dissipation
108
mW
AVDD = 24 V, outputs unloaded
1
Temperature range: 40°C to +105°C; typical at +25°C.
2
Overranges are nominal; gain and offset are not trimmed as per nominal ranges.
3
Specification includes gain and offset errors, over temperature, and drift after 1000 hours, TA = 125°C.
4
Guaranteed by characterization, but not production tested.
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