REF 1 VDD
參數(shù)資料
型號(hào)： EVAL-CN0194-SDPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/28頁(yè)
文件大小： 0K
描述： BOARD CFTL AD7685
設(shè)計(jì)資源： CN-0194 CFTL Eval/Design Support
標(biāo)準(zhǔn)包裝： 1
系列： Circuits from the Lab™
主要目的： 參考設(shè)計(jì)，隔離式數(shù)據(jù)采集系統(tǒng)
嵌入式： 否
已用 IC / 零件： AD7685，AD8615，ADuM1402
已供物品： 板
AD7685
Rev. C | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF 1
VDD 2
IN+ 3
IN– 4
GND 5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7685
TOP VIEW
(Not to Scale)
02
96
8-
00
4
Figure 5. 10-Lead MSOP Pin Configuration
1
REF
2
VDD
3
IN+
4
IN–
5
GND
10 VIO
9SDI
8SCK
7SDO
6CNV
TOP VIEW
(Not to Scale)
AD7685
02
968
-00
5
NOTES
1. EXPOSED PAD CONNECTED TO GND. THIS
CONNECTION IS NOT REQUIRED TO MEET
THE ELECTRICAL PERFORMANCES.
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 7. Pin Function Descriptions
Pin No
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Analog Input. It is referred to IN. The voltage range, that is, the difference between IN+ and IN, is 0 V to VREF.
4
IN
AI
Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low.
In chain mode, the data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input
to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level
on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
EPAD
Exposed Pad. Exposed pad connected to GND. This connection is not required to meet the electrical
performances.
1AI = analog input, DI = digital input, DO = digital output, and P = power.
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