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參數(shù)資料
| 型號(hào)： | EVAL-ADV7533-SAZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7533 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
ADV7533
Data Sheet
Rev. A | Page 6 of 12
The power supply noise sensitivity of the ADV7533 is frequency dependent. Therefore, the maximum noise limit for the PVDD is
specified in mV rms vs. frequency (see Figure 2).
70
60
50
40
30
20
10
0
1
10
100
1k
10k
09821-
102
N
OIS
E
LIM
IT
(
m
V
r
m
s
)
FREQUENCY (Hz)
Figure 2. PVDD Maximum Noise Limit
MIPI/DSI SPECIFICATIONS
Unless noted, timing and levels comply with MIPI DPHY standards.
Table 2. DSI High Speed (HS) Specifications
Parameters
Symbol
ADV7533
Temp
Test Level
Min
Typ
Max
Unit
DC SPECIFICATIONS
DSI Input Common Mode Voltage
V
CMRX
25°C
VII
70
330
mV
DSI Input High Threshold
V
IDTH
25°C
VII
70
mV
DSI Input Low Threshold
V
IDTL
25°C
VII
70
mV
DSI Single-Ended Input High Voltage
V
IHHS
25°C
VII
460
mV
DSI Single-Ended Input Low Voltage
V
ILHS
25°C
VII
40
mV
DSI Single-Ended Threshold for Termination Enable
V
TERM-EN
25°C
VII
450
mV
Differential Input Impedance
Z
ID
25°C
VII
80
100
125
Ω
AC SPECIFICATIONS
Single Channel Data Rate
25°C
IV
200
800
Mbps
Data to Clock Setup Time
t
SETUP
25°C
VII
0.15
UI
INST
Data to Clock Hold Time
t
HOLD
25°C
VII
0.15
UI
INST
DSI Clock Duty Cycle
25°C
VII
45
50
55
%
Common-Mode Interference Beyond 450 MHz
V
CMRX(HF)
25°C
VII
100
mV
Common-Mode Interference 50 MHz to 450 MHz
V
CMRX(LF)
25°C
VII
50
+50
mV
Common-Mode Termination
C
CM
25°C
VII
60
pF
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