參數(shù)資料
型號(hào)： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/96頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計(jì)資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 18 of 96
Pin No.
Mnemonic
Type1
Description
A9
NC
No Connect.
A11
NC
No Connect.
A10
NC
No Connect.
B12
NC
No Connect.
B11
NC
No Connect.
B10
AGND
S
Analog Ground.
B9
AGND
S
Analog Ground.
M1
AGND
S
Analog Ground.
M6
AGND
S
Analog Ground.
L1
AVDD
S
Analog Supply (3.3 V).
M7
AVDD
S
Analog Supply (3.3 V).
M12
AGND
S
Analog Ground.
B6
AGND
S
Analog Ground.
L12
AVDD
S
Analog Supply (3.3 V).
C7
NC
No Connect.
B7
REG_PWR
S
Output of 2.5 V On-Chip Regulator. A 470 nF capacitor to DGND must be connected to
this pin.
G1
LVDD
S
Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be
connected to this pin.
G12
LVDD
S
Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be
connected to this pin.
F1
DGND
S
Digital ground.
F12
DGND
S
Digital ground.
H1
IOVDD
S
3.3 V GPIO Supply.
J1
IOGND
S
3.3 V GPIO Ground.
H12
IOVDD
S
3.3 V GPIO Supply.
J12
IOGND
S
3.3 V GPIO Ground.
G2
XTALO
DO
Output from the Crystal Oscillator Inverter. If an external crystal is not being used, this
pin can be left unconnected.
H2
XTALI
DI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits. If an external crystal is not being used, this pin should be connected to the
DGND system ground.
D10
TDO/P1.3/PLAO[14]
DO
JTAG Test Port Output, Test Data Out (TDO). Debug and download access.
General-Purpose Input and Output Port 1.3 (P1.3).
Output of PLA Element 14 (PLAO[14]). This pin should not be used as a GPIO when
debugging via the JTAG interface.
C10
TDI/P1.2/PLAO[15]
DI
JTAG Test Port Input, Test Data In (TDI). Debug and download access.
General-Purpose Input and Output Port 1.2 (P1.2).
Output of PLA Element 15 (PLAO[15]). This pin should not be used as a GPIO when
debugging via the JTAG interface.
F10
TCK
DI
JTAG Test Port Input, Test Clock. Debug and download access.
E10
TMS
DI
JTAG Test Port Input, Test Mode Select. Debug and download access.
1 I = input, I/O = input/output, AI/O = analog input/output, NC = no connect, AO = analog output, AI = analog input, DI = digital input, DO = digital output, S = supply.
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