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參數(shù)資料
| 型號： | EVAL-ADF4350EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD 1 FOR ADF4350 |
| 設計資源： | Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4350 |
| 主要屬性： | 帶 VCO 的單路分數(shù)-N 和整數(shù)-N PLL |
| 次要屬性： | USB 接口 |
| 已供物品： | 板，纜線，CD |
| 其它名稱： | Q4437453 Q4841122 Q5095480 Q5242312 Q5416250 |
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ADF4350
Rev. A | Page 12 of 32
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4350 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (for details,
block diagram form.
DGND
DVDD
CONTROL
MUX
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
RESERVED
THREE-STATE OUTPUT
DVDD
Figure 19. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4350 digital section includes a 10–bit RF R counter,
a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit
modulus counter. Data is clocked into the 32–bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. These are the 3 LSBs, DB2, DB1, and DB0, as shown
in Figure 2. The truth table for these bits is shown in Table 5.
Figure 23 shows a summary of how the latches are programmed.
Table 5. C3, C2, and C1 Truth Table
Control Bits
C3
C2
C1
Register
0
Register 0 (R0)
0
1
Register 1 (R1)
0
1
0
Register 2 (R2)
0
1
Register 3 (R3)
1
0
Register 4 (R4)
1
0
1
Register 5 (R5)
PROGRAM MODES
modes are to be set up in the ADF4350.
A number of settings in the ADF4350 are double buffered.
These include the modulus value, phase value, R counter value,
reference doubler, reference divide-by-2, and current setting.
This means that two events have to occur before the part uses
a new value of any of the double buffered settings. First, the
new value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R0.
For example, any time the modulus value is updated, Register 0
(R0) must be written to, to ensure the modulus value is loaded
correctly. Divider select in Register 4 (R4) is also double buf-
fered, but only if DB13 of Register 2 (R2) is high.
VCO
The VCO core in the ADF4350 consists of three separate VCOs
each of which uses 16 overlapping bands, as shown in Figure 20,
to allow a wide frequency range to be covered without a large
VCO sensitivity (KV) and resultant poor phase noise and spu-
rious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic at power-up or whenever Register 0
(R0) is updated.
VCO and band selection take 10 PFD cycles × band select clock
divider value. The VCO VTUNE is disconnected from the output
of the loop filter and is connected to an internal reference voltage.
2.8
2.4
2.0
1.6
0.8
1.2
0.4
0
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
07
32
5-
0
09
FREQUENCY (MHz)
V
TU
NE
(V
)
Figure 20. VTUNE vs. Frequency
The R counter output is used as the clock for the band select
logic. A programmable divider is provided at the R counter
output to allow division by 1 to 255 and is controlled by
Bits [BS8:BS1] in Register 4 (R4). When the required PFD
frequency is higher than 125 kHz, the divide ratio should be
set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal
value of KV is 33 MHz/V when the N-divider is driven from the
VCO output or this value divided by D. D is the output divider
value if the N-divider is driven from the RF divider output
(chosen by programming Bits [D12:D10] in Register 4 (R4).
The ADF4350 contains linearization circuitry to minimize
any variation of the product of ICP and KV to keep the loop
bandwidth constant.
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| EVAL-ADF4350EB2Z | 功能描述:EVALUATION BOARD 2 FOR ADF4350 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADF4351EB1Z | 功能描述:BOARD 1 EVAL FOR ADF4351 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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