參數(shù)資料
型號(hào)： EVAL-ADAV4622EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 14/28頁
文件大?。?/td> 0K
描述： BOARD EVAL ADAV4622
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： ADAV4622
已供物品： 板
相關(guān)產(chǎn)品： ADAV4622BSTZ-ND - IC AUD PRO ATV/SIF DECODE 80LQFP
ADAV4622
Rev. B | Page 21 of 2
8
FUNCTIONAL DESCRIPTIONS
SIF PROCESSOR
Supported SIF Standards
The ADAV4622 supports all worldwide standards, as shown in
Table 6. ADAV4622 Worldwide SIF Standards
System
Sound
SC1 (MHz)
SC2 (MHz)
M
BTSC
4.5
–
N
BTSC
4.5
–
M
EIAJ
4.5
–
M
A2
4.5
4.724
BG
A2
5.5
5.742
BG
NICAM
5.5
5.85
I
Mono
6.0
–
I
NICAM
6.0
6.552
DK1
A2
6.5
6.258
DK2
A2
6.5
6.742
DK3
A2
6.5
5.742
DK
NICAM
6.5
5.85
L
Mono
6.5
–
L
NICAM
6.5
5.85
SIF Demodulation
Figure 22 shows a block diagram of the SIF demodulation
block. The selected SIF input signal is digitized by an ADC with
a sample rate of 24.576 MHz. An AGC is included to ensure
that for even low level signals, the full range of the ADC is used.
The digitized input is passed to the SIF demodulator for
demodulating. The outputs of the demodulator are then passed
to the internal audio processor. Internally, the audio processor
runs at a 48 kHz sampling frequency. When NICAM is selected,
an internal SRC upsamples the 32 kHz NICAM signal to the
audio processor rate of 48 kHz.
SIF Processor Configuration
The ADAV4622 supports automatic standard detection, which
is enabled by default. The ASD controller configures the SIF
processor with the optimum register settings based on the
detected standard. If the user prefers to operate in manual mode,
or if the user prefers to use an external ASD loop, all of the ASD
status registers are available.
MASTER CLOCK OSCILLATOR
Internally, the ADAV4622 operates synchronously to the master
MCLKI input. All internal system clocks are generated from
this single clock input using an internal PLL. This MCLKI input
can also be generated by an external crystal oscillator connected
to the MCLKI/XIN pin or by using a simple crystal resonator
connected across MCLKI/XIN and XOUT. By default, the
master clock frequency is 24.576 MHz; however, by using the
internal dividers, an MCLKI of 12.288 MHz, 6.144 MHz, and
3.072 MHz are also supported.
OSC
DIVIDER
REGISTER
DIVIDER WORD
[÷8, ÷4, ÷2, ÷1]
3.072MHz
PLL
REFERENCE
CLOCK
MASTER CLOCK FREQUENCY
[24.576MHz, 12.288MHz,
6.144MHz, 3.072MHz]
I2C
EXTERNAL CLOCK/
CRYSTAL
0706
8-
018
Figure 21. Master Clock
SIF_IN2
SIF_IN1
SIF INPUT
4.5MHz ~ 6.742MHz
MU
X
AGC
ADC
24.576MHz
FM/DQPSK/AM
DEMOD
SC1
SC2
A
B
SIF
PARAMETERS
ASD
07
06
8-
0
20
Figure 22. SIF Demodulation
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