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參數(shù)資料
| 型號： | EVAL-ADAU1966Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1966 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 16 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | I²S，串行，SPI? |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADAU1966 |
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ADAU1966
Data Sheet
Rev. D | Page 22 of 52
Table 22. Pin Function Changes in Different Serial Audio Interface Modes
Signal
Stereo Modes
(SAI = 0 or 1)
TDM4 Mode
(SAI = 2)
TDM8 Mode
(SAI = 3)
TDM16 Mode
(SAI = 4)
DSDATA1
Channel 1/Channel 2
data in
Channel 1 to Channel 4
data in
Channel 1 to Channel 8
data in
Channel 1 to Channel 16
data in
DSDATA2
Channel 3/Channel 4
data in
Channel 5 to Channel 8
data in
Channel 9 to Channel 16
data in
Not used
DSDATA3
Channel 5/Channel 6
data in
Channel 9 to Channel 12
data in
Not used
DSDATA4
Channel 7/Channel 8
data in
Channel 13 to Channel 16
data in
Not used
DSDATA5
Channel 9/Channel 10
data in
Not used
DSDATA6
Channel 11/Channel 12
data in
Not used
Not Used
Not used
DSDATA7
Channel 13/Channel 14
data in
Not used
DSDATA8
Channel 15/Channel 16
data in
Not used
DLRCLK
DLRCLK in/DLRCLK out
TDM frame sync in/
TDM frame sync out
TDM frame sync in/
TDM frame sync out
TDM frame sync in/
TDM frame sync out
DBCLK
DBCLK in/DBCLK out
TDM DBCLK in/TDM
DBCLK out
TDM DBCLK in/TDM
DBCLK out
TDM DBCLK in/
TDM DBCLK out
Maximum Sample Rate
192 kHz
96 kHz
48 kHz
ADDITIONAL MODES
The ADAU1966 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit DBCLK. See
Figure 20 for an example of a DAC TDM data transmission mode
that does not require a high speed DBCLK or an external MCLK.
This configuration is applicable when the ADAU1966 master
clock is generated by the PLL with the DLRCLK as the PLL
reference frequency.
To relax the requirement for the setup time of the ADAU1966 in
cases of high speed TDM data transmission, the ADAU1966 can
latch in the data using the falling edge of DBCLK; see the
BCLK_EDGE bit in the DAC_CTRL1 register. This effectively
dedicates the entire BCLK period to the setup time. This mode
is useful in cases where the source has a large delay time in the
serial data driver. Figure 21 shows this inverted DBCLK mode
of data transmission.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
| EVAL-ADAU1978Z | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Analog-to-Digital Converter (ADC) |
| EVAL-ADAU7002Z | 功能描述:音頻 IC 開發(fā)工具 ADAU7002 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| EVAL-ADAV400EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For Audio Codec With Embedded Sigmadsp Processor 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C - Bulk |
| EVAL-ADAV4422EBZ | 功能描述:BOARD EVALUATION FOR ADAV4422 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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