參數(shù)資料
型號(hào)： EVAL-AD7946SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7946
標(biāo)準(zhǔn)包裝： 1
系列： *
AD7946
Rev. A | Page 23 of 24
APPLICATION GUIDELINES
LAYOUT
The printed circuit board that houses the AD7946 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7946, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7946 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7946s.
The AD7946 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the power supplies VDD and VIO of the AD7946
should be decoupled with ceramic capacitors (typically 100 nF)
placed close to the AD7946 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of layout following these rules is shown in
EVALUATING THE AD7946’S PERFORMANCE
Other recommended layouts for the AD7946 are outlined
in the documentation of the evaluation board for the AD7946
(EVAL-AD7946CB). The evaluation board package includes a
fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
04656-044
Figure 45. Example of Layout of the AD7946 (Top Layer)
04656-045
Figure 46. Example of Layout of the AD7946 (Bottom Layer)
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