參數(shù)資料
型號： EVAL-AD7922CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 19/32頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7922
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ Vdd
在以下條件下的電源（標(biāo)準(zhǔn)）： 15.5mW @ 1MSPS，5 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7922
已供物品： 板，CD
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AD7922ARMZ-REEL-ND - IC ADC DUAL 12BIT 2CH 8MSOP
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AD7912/AD7922
Rev. 0 | Page 26 of 32
MICROPROCESSOR INTERFACING
The serial interface on the AD7912/AD7922 allows the parts to
be directly connected to a range of microprocessors. This
section explains how to interface the AD7912/AD7922 with
some of the more common microcontroller and DSP serial
interface protocols.
AD7912/AD7922 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7912/AD7922. The CS input allows easy interfacing between
the TMS320C541 and the AD7912/AD7922 without any glue
logic required. The serial port of the TMS320C541 is set up to
operate in burst mode (FSM = 1 in the serial port control
register, SPC) with the internal serial clock CLKX (MCM = 1 in
the SPC register) and the internal frame signal (TXM = 1 in the
SPC register); therefore, both pins are configured as outputs. For
the AD7922, the word length should be set to 16 bits (FO = 0 in
the SPC register). This DSP allows frames with a word length of
16 bits or 8 bits only. In the AD7912, therefore, where 14 bits are
required, the FO bit should be set up to 16 bits, and 16 SCLKs
are needed. For the AD7912, two trailing zeros are clocked out
in the last two clock cycles.
The values in the SPC register are as follows:
FO = 0
FSM = 1
MCM = 1
TXM = 1
To implement the power-down mode on the AD7912/AD7922,
the format bit, FO, can be set to 1, which sets the word length to
8 bits.
The connection diagram is shown in Figure 39. Note that, for
signal processing applications, the frame synchronization signal
from the TMS320C541 must provide equidistant sampling.
AD7912/
AD7922*
TMS320C541*
CLKX
DR
FSX
FSR
SCLK
DOUT
CS
CLKR
DX
DIN
04351-0-036
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 39. Interfacing to the TMS320C541
AD7912/AD7922 to ADSP-218x
The ADSP-218x family of DSPs are interfaced directly to the
AD7912/AD7922 without any glue logic required. The SPORT
control register should be set up as follows:
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right-justify data
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0, set up RFS as an input
ITFS = 1, set up TFS as an output
SLEN = 1111, 16 bits for the AD7922
SLEN = 1101, 14 bits for the AD7912
To implement the power-down mode, SLEN should be set to
0111 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 40. The ADSP-218x has the TFS and RFS of the
SPORT tied together, with TFS set as an output and RFS set as
an input. The DSP operates in alternate framing mode and the
SPORT control register is set up as described previously. The
frame synchronization signal generated on the TFS is tied to CS
and, as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt is used to control the sampling rate of the ADC and,
under certain conditions, equidistant sampling might not be
achieved.
AD7912/
AD7922*
ADSP-218x*
SCLK
RFS
TFS
SCLK
CS
DR
DOUT
DT
DIN
04351-0-037
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 40. Interfacing to the ADSP-218x
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, that is, TX0 = AX0, the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, the data might be transmitted or
it might wait until the next clock edge.
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