- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17035 > EVAL-AD7912CBZ (Analog Devices Inc)BOARD EVALUATION FOR AD7912 PDF資料下載
參數(shù)資料
| 型號： | EVAL-AD7912CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7912 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ Vdd |
| 在以下條件下的電源（標準）： | 1MSPS 帶 3V 電壓時為 4.8mW |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7912 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7912ARMZ-ND - IC ADC 10BIT DUAL 2CH 8MSOP AD7912AUJZ-REEL7TR-ND - IC ADC 10BIT DUAL 2CH TSOT-23-8 AD7912ARMZ-REEL7-ND - IC ADC 10BIT DUAL 2CH 8MSOP AD7912AUJZ-REEL-ND - IC ADC 10BIT DUAL 2CH TSOT-23-8 AD7912ARMZ-REEL-ND - IC ADC 10BIT DUAL 2CH 8MSOP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD7912/AD7922
Rev. 0 | Page 25 of 32
SERIAL INTERFACE
serial interfacing to the AD7922 and AD7912, respectively. The
serial clock provides the conversion clock and also controls the
transfer of information from the AD7912/AD7922 during
conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state. The analog input is sampled at
this point and the conversion is initiated.
For the AD7922, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 37 at Point B. On the 16th SCLK falling edge,
the DOUT line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, then the conversion is
terminated and the DOUT line goes back into three-state.
Otherwise, DOUT returns to three-state on the 16th SCLK
falling edge, as shown in Figure 37. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7922.
For the AD7912, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 38 at Point B.
If the rising edge of CS occurs before 14 SCLKs have elapsed,
then the conversion is terminated and the DOUT line goes back
into three-state. If 16 SCLKs are considered in the cycle, DOUT
returns to three-state on the 16th SCLK falling edge, as shown
in Figure 38.
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Therefore, the first falling clock edge on
the serial clock has the first leading zero provided and also
clocks out the second leading zero. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In that case, the first falling edge of
SCLK clocks out the second leading zero and it can be read in
the first rising edge. However, the first leading zero that is
clocked out when CS goes low is missed, unless it is read on the
first falling SCLK edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If CS goes low just after the SCLK falling edge has elapsed, CS
clocks out the first leading zero as before and it can be read in
the SCLK rising edge. The next SCLK falling edge clocks out
the second leading zero and it can be read in the following
rising edge.
04351-0-034
ZERO
X
12
34
5
13
14
15
16
X
CHN
STY
X
CHN
MOD
DB11
DB10
DB2
DB1
DB0
Z
t2
t6
t4
t8
t9
t3
t7
t5
t10
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-STATE
DIN
B
Figure 37. AD7922 Serial Interface Timing Diagram
04351-0-035
ZERO
X
12
34
5
13
14
15
16
X
CHN
STY
X
CHN
MOD
DB9
DB8
DB0
ZERO
Z
t2
t6
t4
t8
t9
t3
t7
t5
t10
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-STATE
TWO TRAILING ZEROS
DIN
B
Figure 38. AD7912 Serial Interface Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| REC5-053.3SRW/H6/C | CONV DC/DC 5W 4.5-9VIN 3.3VOUT |
| LLS2D821MELA | CAP ALUM 820UF 200V 20% SNAP |
| EVAL-AD7912CB | BOARD EVALUATION FOR AD7912 |
| REC5-053.3SRW/H6/A | CONV DC/DC 5W 4.5-9VIN 3.3VOUT |
| VE-21J-EY | CONVERTER MOD DC/DC 36V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7920CB | 制造商:AD 制造商全稱:Analog Devices 功能描述:250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 |
| EVAL-AD7920CBZ | 功能描述:BOARD EVALUATION FOR AD7920 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7922CB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7922CBZ | 功能描述:BOARD EVAL FOR AD7922 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7923CB2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。