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參數(shù)資料
| 型號(hào)： | EVAL-AD7839EBZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7839 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 8 |
| 位數(shù)： | 13 |
| 采樣率（每秒）： | 33k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 30µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，纜線(xiàn)，CD |
| 已用 IC / 零件： | AD7839 |
| 相關(guān)產(chǎn)品： | AD7839ASZ-REEL-ND - IC DAC 13BIT OCT VOLT OUT 44MQFP AD7839ASZ-ND - IC DAC 13BIT OCTAL V-OUT 44-MQFP |
–3–
REV. 0
AD7839
(These characteristics are included for Design Guidance and are not subject
to production testing.)
AC PERFORMANCE CHARACTERISTICS
Parameter
A
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
30
s typ
Full-Scale Change to
±1/2 LSB. DAC Latch Contents Alternately
40
s max
Loaded with All 0s and All 1s
Slew Rate
0.7
V/
s typ
Digital-to-Analog Glitch Impulse
230
nV-s typ
Measured with VREF(+) = +5 V, VREF(–) = –5 V. DAC Latch
Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent
on Load Conditions
Channel-to-Channel Isolation
99
dB typ
See Terminology
DAC-to-DAC Crosstalk
40
nV-s typ
See Terminology
Digital Crosstalk
0.2
nV-s typ
Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Digital Feedthrough
0.1
nV-s typ
Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density
@ 1 kHz
200
nV/
√Hz typ
All 1s Loaded to DAC. VREF(+) = VREF(–) = 0 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS1, 2
Parameter
Limit at TMIN, TMAX
Units
Description
t1
15
ns min
Address to
WR Setup Time
t2
0
ns min
Address to
WR Hold Time
t3
50
ns min
CS Pulsewidth Low
t4
50
ns min
WR Pulsewidth Low
t5
0
ns min
CS to WR Setup Time
t6
0
ns min
WR to CS Hold Time
t7
20
ns min
Data Setup Time
t8
0
ns min
Data Hold Time
t9
30
s typ
Settling Time
t10
300
ns max
CLR Pulse Activation Time
t11
50
ns min
LDAC Pulsewidth Low
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t1
t2
t5
t6
t3
t4
t7
t8
t9
t10
LDAC
CLR
WR
CS
A0, A1, A2
DATA
VOUT
t11
Figure 1. Timing Diagram
(VCC = +5 V
5%; VDD = +15 V
5%; VSS = –15 V
5%; GND = DUTGND = 0 V)
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