參數(shù)資料
型號: EVAL-AD7785EBZ
廠商: Analog Devices Inc
文件頁數(shù): 21/32頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7785
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 20
采樣率(每秒): 470
數(shù)據(jù)接口: 串行
輸入范圍: ±VREF
工作溫度: -40°C ~ 105°C
已用 IC / 零件: AD7785
已供物品: 板,纜線,CD
相關(guān)產(chǎn)品: AD7785BRUZ-REEL-ND - IC ADC 20BIT 3CH LN LP 16-TSSOP
AD7785BRUZ-ND - IC ADC 20BIT SIGMA-DELTA 16TSSOP
AD7785
Rev. 0 | Page 28 of 32
The ground planes of the AD7785 should be allowed to run
under the device to prevent noise coupling. The power supply
lines to the AD7785 should use as wide a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals such as clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and clock signals should never be
run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on oppo-
site sides of the board should run at right angles to each other.
This reduces the effects of feedthrough through the board.
A microstrip technique is by far the best, but it is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes, and
signals are placed on the solder side.
Good decoupling is important when using high resolution
ADCs. AVDD should be decoupled with 10 μF tantalum in
parallel with 0.1 μF capacitors to GND. DVDD should be
decoupled with 10 μF tantalum in parallel with 0.1 μF
capacitors to the system’s DGND plane, with the system’s
AGND to DGND connection being close to the AD7785.
To achieve the best from these decoupling components, they
should be placed as close as possible to the device, ideally right
up against the device. All logic chips should be decoupled with
0.1 μF ceramic capacitors to DGND.
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